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5 - channel integrated power solution with quad buck regulators and 200 ma ldo regulator data sheet ADP5050 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by anal og devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 analog devices, inc. all righ ts reserved. technical support www.analog.com features wide input voltage range: 4.5 v to 15 v 1.5 % output accuracy over full temperature range 250 khz to 1.4 mhz adjustable switching frequency adjustable/fixed output options via factory fuse or i 2 c interface i 2 c interface with interrupt on fau lt con ditions power regulation channel 1 and channel 2: programmable 1.2 a/2.5 a/4 a sync buck regulators with low - side fet driver channel 3 and channel 4: 1.2 a sync buck regulators channel 5: 200 ma low dropout (ldo) regulator single 8 a output (channel 1 and channel 2 operated in parallel) dynamic voltage scaling (dvs) for channel 1 and channel 4 p recision e nable with 0.8 v accurate threshold active output discharge switch p rogrammable phase shift in 90 steps individual channel fpwm/psm mode selection frequen cy synchronization input or output optional latch - off protection on ovp/ocp failure power - good flag on selected channels low input voltage detection overheat detection on junction temperature uvlo, ocp, and tsd protection 48- lead, 7 mm 7 mm lfcsp package ?40c to + 125c junction temperature applications small cell base stations fpga and processor a pplication s security and surveillance medical applications typical application circuit channel 2 buck regulator (1.2a/2.5a/4a) channel 3 buck regulator (1.2a) oscillator int vreg 100ma q1 q2 l1 l2 vreg sync/mode rt fb1 bst1 sw1 dl1 pgnd dl2 sw2 bst2 fb2 l3 bst3 sw3 fb3 pgnd3 alert l4 bst4 sw4 fb4 pgnd4 nint vreg pvin1 comp1 en1 pvin2 comp2 en2 pvin3 ss34 comp3 en3 vddio pvin4 comp4 en4 scl sda c2 c1 c4 c3 c5 c6 c7 c8 c9 c10 c11 c12 c13 4.5v to 15v vout1 vout2 vout3 vout4 r ilim1 r ilim2 i 2 c pwrgd vreg exposed pad ss12 c0 vdd channel 5 200ma ldo regulator fb5 pvin5 en5 vout5 c14 c15 vout5 1.7v to 5.5v ADP5050 channel 1 buck regulator (1.2a/2.5a/4a) channel 4 buck regulator (1.2a) 10899-001 figure 1. general description the ADP5050 combines four high performance buck regulators and one 200 ma low dropout (ldo) regulator in a 48 - lead lfcsp package that meets demanding performance and board space requirements. the device enab les direct connection to high input voltages up to 15 v with no preregulators. channel 1 and channel 2 integrate high - side power mosfets and low - side mosfet drivers. external nfets can be used in low - side power devices to achieve an efficiency optimized so lution and deliver a programmable output current of 1.2 a, 2.5 a, or 4 a. combining channel 1 and channel 2 in a parallel configuration can provide a single output with up to 8 a of current. channel 3 and channel 4 integrate both high - side and low - side mos fets to deliver output current of 1.2 a. the switching frequency of the ADP5050 can be programm ed or synchronized to an external clock. the ADP5050 contains a precision enable pin on each channel for easy power - up sequencing or adjustable uvlo threshold. the ADP5050 integrates a general - purpose ldo regulator with low quiescent current and low dropout voltage that provides up to 200 ma of output current. the optional i 2 c interface provides the user with flexible configuration options, including adjustable and fixed output voltage options, junction temperature overheat warning, lo w input voltage detection, and dynamic voltage scaling (dvs).
ADP5050 data sheet rev. 0 | page 2 of 60 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 typical application circuit ............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 3 detailed functional block diagram .............................................. 4 specifications ..................................................................................... 5 buck regulator specification s .................................................... 6 ldo regulator specifications .................................................... 8 i 2 c interface timing specifications ........................................... 9 absolute maximum ratings .......................................................... 10 thermal resistance .................................................................... 10 esd caution ................................................................................ 10 pin configuration and function descriptions ........................... 11 typical performance characteristics ........................................... 13 theory of operation ...................................................................... 19 buck regulator operational modes ......................................... 19 adjustable and fixed output voltages .................................... 20 dynamic voltage scaling (dvs) .............................................. 20 internal regulators (vreg and vdd) ................................... 20 separate supply applications .................................................... 20 low - side device selection ........................................................ 21 bootstrap circuitry .................................................................... 21 active output discharge switch .............................................. 21 precision enabling ...................................................................... 21 oscillator ..................................................................................... 21 synchronization input/output ................................................. 22 soft start ...................................................................................... 23 parallel operation ....................................................................... 23 startup with precharged output .............................................. 23 current - limit protection .......................................................... 24 frequency foldback ................................................................... 24 hicc up protection ...................................................................... 24 latch - off protection .................................................................. 24 undervoltage lockout (uvlo) ............................................... 25 power - good function ............................................................... 25 interrupt function ...................................................................... 25 thermal shutdown .................................................................... 26 overheat detection .................................................................... 26 low input voltage detection .................................................... 26 ldo regulator ........................................................................... 26 i 2 c interface .................................................................................... 27 sda and scl pins ...................................................................... 27 i 2 c addresses .............................................................................. 27 self - clear register bits .............................................................. 27 i 2 c interface timing diagrams ................................................ 28 applications information .............................................................. 29 adisimpower design tool ....................................................... 29 programming the adjustable output voltage ........................ 29 voltage conversion limi tations ............................................... 29 current - limit setting ................................................................ 29 soft start setting ......................................................................... 30 induct or selection ...................................................................... 30 output capacitor selection ....................................................... 30 input capacitor selection .......................................................... 31 low - side power device selection ............................................ 31 programming the uvlo input ................................................ 31 compensation components design ....................................... 32 power dissipation ....................................................................... 32 junction temperature ................................................................ 33 design example .............................................................................. 34 setting the switching frequency .............................................. 34 setting the output voltage ........................................................ 34 setting the curren t limit .......................................................... 34 selecting the inductor ................................................................ 34 selecting the output capacitor ................................................ 35 selecting the low - side mosfet ............................................. 35 designing the compensation network ................................... 35 selecting the soft start time ..................................................... 35 selecting the input capacitor ................................................... 35 recommended external components .................................... 36 circuit board layout recommendations ................................... 37 typical application circuits ......................................................... 38 register map ................................................................................... 41
data sheet ADP5050 rev. 0 | page 3 of 60 detailed register descriptions ...................................................... 42 register 1: pctrl (channel enable control), address 0x01 ................................................................................ 42 register 2: vid1 (v id setting for channel 1), address 0x02 ................................................................................ 42 register 3: vid23 (vid setting for channel 2 and channel 3), address 0x03 ................................................... 43 regist er 4: vid4 (vid setting for channel 4), address 0x04 ................................................................................ 43 register 5: dvs_cfg (dvs configuration for channel 1 and channel 4), address 0x05 ......................... 44 register 6: opt_cfg (fpwm/psm mode and output discharge function configuration), address 0x06 ................ 45 register 7: lch_cfg (short - circuit latch - off and overvoltage latch - off configura tion), address 0x07 .......... 46 register 8: sw_cfg (switching frequency and phase shift configuration), address 0x08 ....................... 47 register 9: th_c fg (temperature warning and low v in warning threshold configuration), address 0x09 ......... 48 register 10: hiccup_cfg (hiccup configuration), address 0x0a .................................................. 49 register 11: pwrgd_mask (channel mask configuration for pwrgd pin), address 0x0b ..................... 50 register 12: lch_status (latch - off status readback), address 0x0c .......................................................... 51 register 13: status_rd (status readback), address 0x0d .............................................................................. 51 register 14: int_status (interrupt status readback), address 0x0e ........................................................... 52 register 15: int_mask (interrupt mask configuration), address 0x0f ................................................... 53 register 17: default_set (default reset), address 0x11 ................................................................................ 53 factory programmable options .................................................... 54 factory default options ............................................................. 56 outline dimensi ons ........................................................................ 57 ordering guide ........................................................................... 57 revision history 5 /1 3 revision 0: initial version
ADP5050 data sheet rev. 0 | page 4 of 60 detailed functional block diagram q1 q dg1 q pwrgd q dg3 uvlo1 pvin1 sw1 bst1 vreg vreg driver driver pgnd dl1 control logic and mosfet driver with anticross protection control logic and mosfet driver with anticross protection en1 0.8v 1m? hiccup and latch-off ocp comp1 fb1 0.8v clk1 slope comp clk1 0.72v pwrgd1 zero cross current-limit selection frequency foldback + ? + ? + ? ? + + ? + ? + ? channel 1 buck regulator duplicate channel 1 channel 2 buck regulator current balance en2 comp2 fb2 dl2 pvin2 sw2 bst2 discharge switch vid1 0.99v ovp latch-off ea1 cmp1 rt oscillator sync/mode soft start decoder ss12 ss34 vdd vreg internal regulator pvin1 vddio scl sda i 2 c interface and registers vreg power-on reset pwrgd housekeeping logic nint uvlo3 pvin3 sw3 bst3 vreg vreg driver q3 q4 driver pgnd3 en3 comp3 fb3 channel 3 buck regulator duplicate channel 3 channel 4 buck regulator en4 comp4 fb4 pgnd4 pvin4 sw4 bst4 a cs1 + ? ? + a cs3 q7 pvin5 vout5 en5 ldo control fb5 0.5v channel 5 ldo regulator 0.8v 1m? + ? discharge switch 0.8v 1m? hiccup and latch-off ocp 0.8v clk3 slope comp clk3 0.72v pwrgd3 frequency foldback + ? + ? + ? ? + + ? + ? vid3 0.99v ovp latch-off ea3 cmp3 zero cross ea5 10899-202 figure 2.
data sheet ADP5050 rev. 0 | page 5 of 60 specifi cations v in = 12 v, v vreg = 5 .1 v, t j = ?40 c to +125 c for minimum and maximum specifications , and t a = 25 c for typical specifications, unless otherwise noted . table 1 . parameter symbol min typ max unit test conditions/comments input supply voltage range v in 4.5 15.0 v pvin1, pvin2, pvin3, pvin4 pins quiescent current pvin1, pvin2, pvin3, pvin4 pins operating quiescent current i q(4 - bucks ) 4.8 6.25 ma no switching, all enx pins high i shdn(4bucks+ldo) 25 65 a all enx p ins low undervoltage lockout uvlo pvin1, pvin2, pvin3, pvin4 pins rising threshold v uvlo - rising 4.2 4. 36 v falling threshold v uvlo - falling 3.6 3.78 v hysteresis v hys 0.42 v oscillator circuit switching frequency f sw 700 740 780 khz r t = 25.5 k? switching frequency r ange 250 1400 khz sync input input clock range f sync 250 1400 khz input clock pulse width min imum on time t sync_ min _on 100 ns min imum o ff time t sync_ min _ off 100 ns input clock high voltage v h(s ync) 1.3 v input clock low voltage v l (sync) 0.4 v sync output clock frequency f clk f sw khz positive pulse duty cycle t clk_ pulse _ duty 50 % rise or fall time t clk_ rise _ fal l 10 ns high level voltage v h(sync _out ) v vr eg v precisio n enabling en1, en2, en3, en4, en5 pins high level threshold v th_h(en) 0.80 6 0.8 32 v low level threshold v th_l(en) 0.688 0.72 5 v pull - down resistor r pull - down (en) 1.0 m? power good internal power - good rising threshold v pwrgd(rise) 86.3 90.5 95 % internal p ower - g ood hysteresis v pwrgd(hys) 3 .3 % internal p ower - g ood falling delay t pwrgd_ fal l 50 s rising delay for pwrgd pin t pwrgd_ pin _ rise 1 ms leaka ge current for pwrgd pin i pwrgd_ leakage 0.1 1 a output low voltage for pwrgd pin v pwrgd_low 50 100 mv i pwrgd = 1 ma logic inputs (scl and sda pins) vddio = 3.3 v high level threshold v logic _ high 0.7 vddio v low level threshold v logic _ low 0.3 vddio v logic outputs low level output voltage sda pin v sda _ low 0.4 v vddio = 3.3 v, i sda = 3 ma nint pin v nint _ low 0.4 v i nint = 3 ma internal regulator s vdd output voltage v vdd 3.2 3.305 3.4 v i vdd = 10 ma v dd curren t limit i lim _vdd 20 51 80 ma vreg output voltage v vr eg 4.9 5.1 5.3 v vreg dropout voltage v dropout 225 mv i vr eg = 50 ma vreg current limit i lim _v reg 50 95 140 ma
ADP5050 data sheet rev. 0 | page 6 of 60 parameter symbol min typ max unit test conditions/comments low input voltage detection low input voltage threshold v lvin - th 4.07 4.236 4. 39 v lvin_th[3:0] = 0000 10.05 10.25 10.4 v lvin_th[3:0] = 1100 low input voltage threshold range 4.2 11.2 v i 2 c programmable (4 - bit value) thermal shutdown thermal shutdown threshold t shdn 150 c thermal shutdown hysteresis t hys 15 c thermal overheat warning thermal overheat threshold t hot 115 c temp_th[1:0] = 10 overheat threshold range 105 125 c i 2 c programmable (2 - bit value) thermal overheat hysteresis t hot(hys) 5 c buck r egulator specifications v in = 12 v, v v reg = 5.1 v, f sw = 600 khz for all channels, t j = ?40c to +125c for minimum and maximum specifications, and t a = 25c for typical specifications, unless otherwise noted. table 2 . parameter symbol min typ max unit test conditions/comments channel 1 sync buck regulator fb1 pin fixed output options v out1 0.85 1.60 v fuse trim or i 2 c interface (5 - bit value) adjustable feedback voltage v fb1 0.800 v feedback voltage accuracy v fb1(d e fault ) ?0.5 5 +0.5 5 % t j = 25c ?1. 2 5 +1. 0 % 0c t j 8 5c ?1.5 +1. 5 % ?4 0c t j +12 5c feedback bias current i fb1 0.1 a adjustable v oltage sw1 pin high - side power fet on resistance r ds on( 1h ) 100 m? p in - to - pin measurement current - limit threshold i th(ilim1) 3.50 4.4 5.28 a r il im1 = f loating 1.91 2. 63 3.0 8 a r il im1 = 47 k ? 4.95 6.4 4 7.48 a r il im1 = 22 k ? minimum on time t min _ on1 1 17 155 ns f sw = 250 khz to 1.4 mhz minimum off time t min _o ff1 1/9 t sw ns f sw = 250 khz to 1.4 mhz low - side driver, dl1 pin rising time t rising1 20 ns c iss = 1. 2 nf falling time t falling1 3.4 ns c iss = 1. 2 nf sourcing resistor t sourcing1 10 ? sinking resistor t sinking1 0.95 ? error amplifier (ea) , comp1 pin ea transc onductance g m 1 310 470 620 s soft start soft start time t ss1 2.0 ms ss12 connected to vreg programmable soft start range 2.0 8.0 ms hiccup time t hiccup1 7 t ss1 ms c out discharge switch on resistance r dis1 25 0 ?
data sheet ADP5050 rev. 0 | page 7 of 60 parameter symbol min typ max unit test conditions/comments channel 2 sync buck regulator fb2 pin fixed output options v out 2 3.3 5.0 v fuse tr im or i 2 c interface (3 - bit value) adjustable feedback voltage v fb 2 0.800 v feedback voltage accuracy v fb 2 (d e fault ) ?0.5 5 +0.5 5 % t j = 25c ?1. 2 5 +1.0 % 0c t j 8 5c ?1.5 +1.5 % ?40c t j +125c feedback bias current i fb 2 0.1 a adju stable v oltage sw2 pin high - side power fet on resistance r ds on(2 h) 110 m? p in - to - pin measurement current - limit threshold i th(ilim 2 ) 3.50 4.4 5.28 a r il im2 = f loating 1.91 2. 63 3.08 a r il im2 = 47 k ? 4.95 6.4 4 7.48 a r il im2 = 22 k ? minimum on time t min _on 2 1 17 155 ns f sw = 250 khz to 1.4 mhz minimum off time t min _o ff2 1/9 t sw ns f sw = 250 khz to 1.4 mhz low -s ide driver, dl2 pin rising time t rising 2 20 ns c iss = 1. 2 nf falling time t falling 2 3.4 ns c iss = 1. 2 nf sourcing resistor t sourcing 2 10 ? sinking resistor t sinking 2 0.95 ? error amplifier (ea), comp2 pin ea transc onductance g m 2 310 470 620 s soft start soft start time t ss2 2.0 ms ss12 connected to vreg programmable soft start range 2.0 8.0 ms hiccup time t hicc up 2 7 t ss2 ms c out discharge switch on resistance r dis 2 250 ? channel 3 sync buck regulator fb3 pin fixed output options v out 3 1.20 1.80 v fuse trim or i 2 c interface (3 - bit value) adjustable feedback voltage v fb 3 0.800 v feed back voltage accuracy v fb 3 (d e fault ) ?0.5 5 +0.5 5 % t j = 25c ?1. 2 5 +1.0 % 0c t j 8 5c ?1.5 +1.5 % ?40c t j +125c feedback bias current i fb 3 0.1 a adjustable v oltage sw3 pin high - side power fet on resistance r ds on(3 h) 225 m? p in - to - pin measurement low - side power fet on resistance r ds on(3l) 150 m? p in - to - pin measurement current - limit threshold i th(ilim 3 ) 1.7 2. 2 2.55 a minimum on time t min _on 3 90 120 ns f sw = 250 khz to 1.4 mhz minimum off time t min _o ff3 1/9 t sw ns f sw = 250 khz to 1.4 mhz error amplifier (ea), comp3 pin ea transc onductance g m3 310 470 620 s soft start soft start time t ss3 2.0 ms ss34 connected to vreg programmable soft start range 2.0 8.0 ms hiccup time t hiccup 3 7 t ss3 ms c out discharge switch on resistance r dis 3 250 ?
ADP5050 data sheet rev. 0 | page 8 of 60 parameter symbol min typ max unit test conditions/comments channel 4 sync buck regulator fb4 pin fixed output options v out 4 2.5 5.5 v fuse trim or i 2 c interface (5 - bit value) adjustable feedback voltage v fb 4 0.800 v feedback voltage accuracy v fb 4 (d e fault ) ?0.5 5 +0.5 5 % t j = 25c ?1. 2 5 +1.0 % 0c t j 8 5c ?1.5 +1.5 % ?40c t j +125c feedback bias current i fb4 0.1 a sw4 pin high - side power fet on resistance r ds on(4 h) 225 m? p in - to - pin measurement low - side power fet on resistance r ds on(4l) 150 m? p in - to - pin measurement current - limit threshold i th(ilim 4 ) 1.7 2.2 2.55 a minimum on time t min _on 4 90 120 ns f sw = 250 khz to 1.4 mhz minimum off time t min _o ff4 1/9 t sw ns f sw = 250 khz to 1.4 mhz error amplifier (ea), comp4 pin ea transc onductance g m 4 310 470 620 s soft start soft start time t ss4 2.0 ms ss34 connected to vreg programmable soft start range 2.0 8.0 ms hiccup time t hiccup 4 7 t ss4 ms c out discharge switch on resistance r dis 4 250 ? ldo regulator specif ications v in5 = (v out5 + 0.5 v) or 1.7 v (whichever is greater) to 5.5 v; c in = c out = 1 f; t j = ?40 c to +125c for minimum and maximum specifications , and t a = 25c for typical specifications, unless otherwise noted. table 3 . parameter min typ max unit test conditions/comments input supply voltage range 1.7 5.5 v pvin5 pin operation al supply current bias current for ldo regulator 3 0 130 a i out5 = 200 a 60 170 a i out5 = 10 ma 1 4 5 320 a i out5 = 200 ma voltage feedback (fb5 pin) adjustable feedback voltage 0.500 v feedback voltage accuracy ? 1.0 +1.0 % t j = 2 5c ?1. 6 +1.6 % 0c t j 8 5c ? 2.0 + 2.0 % ?40c t j +125c dropout voltage i out5 = 200 ma 80 mv v out5 = 3.3 v 100 mv v out5 = 2.5 v 180 mv v out5 = 1.5 v current - limit threshold 250 510 ma specified from the o utput voltage drop to 90% of the specified typical value output noise 92 v rms 10 hz to 100 khz, v pvin5 = 5 v, vout5 = 1.8 v power supply rejection ratio v pvin5 = 5 v, vout5 = 1.8 v, i out5 = 1 ma 77 db 10 khz 6 6 db 100 khz
data sheet ADP5050 rev. 0 | page 9 of 60 i 2 c interface timing specification s t a = 25c, v vdd = 3 .3 v, v vddio = 3.3 v, unless otherwise noted. table 4 . parameter min typ max unit description f scl 400 khz scl clock frequency t high 0.6 s scl high time t low 1.3 s scl low time t su, dat 100 ns data setup time t hd, dat 0 0.9 s data hold time 1 t su,sta 0.6 s setup time for a repeated start condition t hd ,sta 0.6 s hold time for a start or repeated start condition t buf 1.3 s bus free time between a stop condition and a start condition t su,sto 0.6 s setup time for a stop condition t r 20 + 0.1c b 2 300 ns rise time of scl and sda t f 20 + 0.1c b 2 300 ns fall time of scl and sda t sp 0 50 ns pulse width of suppressed spike c b 2 400 pf capacitive load for each bus line 1 a master de vice must provide a hold time of at least 300 ns for the sda signal (referred to the v ih minimum of the scl signal) to bridge the undefined region of the scl falling edge. 2 c b is the total capacitance of one bus line in picofarads (pf). timing diagram s s p sr s = start condition sr = repeated start condition p = stop condition scl sda t hd,dat t su,dat t hd,sta t su,sta t su,sto t high t r t f t f t sp t r t low t buf 10899-102 figure 3. i 2 c interface timing diagram
ADP5050 data sheet rev. 0 | page 10 of 60 absolute maximum rat ings table 5 . parameter rating pvin1 to pgnd ?0.3 v to +18 v pvin2 to pgnd ?0.3 v to +18 v pvin3 to pgnd3 ?0.3 v to +18 v pvin4 to pgnd4 ?0.3 v to +18 v pvin5 to gnd ?0.3 v to +6.5 v sw1 to pgnd ?0.3 v to +18 v sw2 to pgnd ?0.3 v to +18 v sw3 to pgnd3 ?0.3 v to +18 v sw4 to pgnd4 ?0.3 v to +1 8 v pgnd to gnd ?0.3 v to +0.3 v pgnd3 to gnd ?0.3 v to +0.3 v pgnd4 to gnd ?0.3 v to +0.3 v bst1 to sw1 ?0.3 v to +6.5 v bst2 to sw2 ?0.3 v to +6.5 v bst3 to sw3 ?0.3 v to +6.5 v bst4 to sw4 ?0.3 v to +6.5 v dl1 to pgnd ?0.3 v to +6.5 v dl2 to pg nd ?0.3 v to +6.5 v ss12, ss34 to gnd ?0.3 v to +6.5 v en1, en2, en3, en4, en5 to gnd ?0.3 v to +6.5 v vreg to gnd ?0.3 v to +6.5 v sync/mode to gnd ?0.3 v to +6.5 v vout5, fb5 to gnd ?0.3 v to +6.5 v rt to gnd ?0.3 v to +3.6 v nint, pwrgd to gnd ?0 .3 v to +6.5 v fb1, fb2, fb3, fb4 to gnd 1 ?0.3 v to +3.6 v fb2 to gnd 2 ?0.3 v to +6.5 v fb4 to gnd 2 ?0.3 v to +7 v comp1, comp2, comp3, comp4 to gnd ?0.3 v to +3.6 v vdd, vddio to gnd ?0.3 v to +3.6 v scl, sda ?0.3 v to vddio + 0.3 v storage temper ate range ?65c to +150c operational junction temperature range ?40c to +125c 1 this rating applies to the adjustable output voltage models of the ADP5050 . 2 this rating applies to the fixe d output voltage models of the ADP5050 . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 6 . thermal resistance package type ja jc unit 48- lead lfcsp 27.87 2.99 c/w esd caution
data sheet ADP5050 rev. 0 | page 1 1 of 60 pin configuration an d function descripti ons 1 2 3 pvin1 pvin1 sw1 4 sw1 5 bst1 6 dl1 7 pgnd 24 pvin2 23 en2 22 comp2 21 fb2 20 pwrgd 19 scl 18 sda 17 vddio 16 fb4 15 comp4 14 en4 13 nint 44 vreg 45 fb3 46 comp3 47 ss34 48 en3 43 sync/mode 42 vdd 41 rt 40 fb1 39 comp1 38 ss12 37 en1 t op view (not to scale) ADP5050 25 bst4 26 pgnd4 27 sw4 28 pvin4 29 pvin5 30 vout5 31 fb5 32 en5 33 pvin3 34 sw3 35 pgnd3 36 bst3 notes 1. the exposed p ad must be connected and soldered t o an externa l ground plane. 8 dl2 9 bst2 10 sw2 1 1 sw2 12 pvin2 10899-002 figure 4 . pin configuration table 7 . pin function descriptions pin no. mnemonic description 1 bst3 high -s ide fet d river p ower s upply for channel 3. 2 pgnd3 power ground for channel 3. 3 sw3 switching n ode o utput for channel 3. 4 pvin3 power i nput for channel 3. connect a bypass capacitor between this pin and ground. 5 en5 enable i nput for channel 5 . an e xternal resistor divi der can be used to set t he turn - on threshold. 6 fb5 feedback s ensing i nput for channel 5 . 7 vout5 power o utput for channel 5 . 8 pvin5 power i nput for channel 5 . connect a bypass capacitor between this pin and ground. 9 pvin4 power i nput for channel 4. connect a bypass capacit or between this pin and ground. 10 sw4 switching n ode o utput for channel 4. 11 pgnd4 power ground for channel 4. 12 bst4 high -s ide fet d river p ower s upply for channel 4. 13 nint interrupt o utput on f ault c ondition. open - drain output port. 14 en4 enabl e input for channel 4. an e xternal resistor divi der can be used to set the turn - on threshold. 15 comp4 error amplifier output for channel 4 . connect an rc network from this pin to ground . 16 fb4 feedback s ensing i nput for channel 4. 17 vddio power supp ly for the i 2 c interface. 18 sda data input/output for the i 2 c interface. open - drain i/o port. 19 scl clock input for the i 2 c interface. 20 pwrgd power - good signal output. this open - drain output is the power - good signal for the select ed channels . this pin can be programmed by the factory to set the i 2 c address of the part; the i 2 c address setting function replaces the power - good function on this pin. for more information, see the i 2 c addresses section. 21 fb2 feedback s ensing i nput for c hannel 2. 22 comp2 error amplifier output for channel 2. connect an rc network from this pin to ground . 23 en2 enable input for channel 2. an e xternal resistor divi der can be used to set the turn - on threshold. 24, 25 pvin2 power i nput for cha nnel 2. connect a bypass capacitor between this pin and ground. 26, 27 sw2 switching n ode o utput for channel 2. 28 bst2 high -s ide fet d river p ower s upply for channel 2. 29 dl2 low -s ide fet g ate d river for channel 2. connect a resistor from this pin to g round to program the current - limit threshold for channel 2.
ADP5050 data sheet rev. 0 | page 12 of 60 pin no. mnemonic description 30 pgnd power g round for channel 1 and channel 2. 31 dl1 low -s ide fet g ate d river for channel 1. connect a resistor from this pin to ground to program the current - limit threshold for channel 1. 32 bst1 high -s ide fet d river p ower s upply for channel 1. 33, 34 sw1 switching n ode o utput for channel 1. 35, 36 pvin1 power input for the internal 5.1 v vreg linear regulator and the channel 1 buck regulator. connect a bypass capacitor between this pin and ground. 37 en1 enable input for channel 1. an e xternal resistor divi der can be used to set the turn - on threshold. 38 ss12 connect a resistor divider from this pin to vreg and ground to configure the s oft start time for channel 1 and channel 2 (see th e soft start section). this pin is also used to configure parallel operation of channel 1 and channel 2 (see the parallel operation section) . 39 comp1 error amplifier output for channel 1 . connect an rc network from this pin to ground . 40 fb1 feedback s ensing i nput for channel 1. 41 rt connect a resistor from rt to ground to program the switching frequency from 250 khz to 1.4 mhz . for more information, see the os cillator section. 42 vdd o utput of the i nternal 3 .3 v linear r egulator. connect a 1 f ceramic capacitor between this pin and ground . 43 sync/mode synchronization input/output (sync). to synchronize the switching frequency of the part to an external clo ck, connect this pin to an external clock with a frequency from 250 khz to 1.4 mhz. this pin can also be configured as a synchronization output using the i 2 c interface or by factory fuse. forced pwm or automatic pwm/psm selection pin (mode). when this pin is logic high, each channel operates in forced pwm or automatic pwm/psm mode, as specified by the psmx_on bits in register 6. when this pin is logic low, all channels operate in automatic pwm/psm mode, and the psmx_on settings in register 6 are ignored. 4 4 vreg o utput of the i nternal 5 .1 v linear r egulator. connect a 1 f ceramic capacitor between this pin and ground . 45 fb3 feedback s ensing i nput for channel 3. 46 comp3 error amplifier output for channel 3. connect an rc network from this pin to ground . 47 ss34 connect a resistor divider from this pin to vreg and ground to configure the s oft start time for channel 3 and channel 4 (see the soft start section). 48 en3 enable input for channel 3. an e xternal resistor divi der can be used to set the turn - on threshold. epad exposed pad ( analog ground ) . the exposed pad must be connected and soldered to an external ground plane.
data sheet ADP5050 rev. 0 | page 13 of 60 typical performance characteristics 0 10 20 30 40 50 60 70 80 90 100 01234 efficiency (%) i out (a) v out =1.2v v out =1.5v v out =1.8v v out =2.5v v out =3.3v v out =5.0v 10899-003 figure 5. channel 1/channel 2 efficiency curve, v in = 12 v, f sw = 600 khz, fpwm mode 0 10 20 30 40 50 60 70 80 90 100 01234 efficien c y (%) i out (a) v out =1.2v v out =1.5v v out =1.8v v out =2.5v v out =3.3v 10899-004 figure 6. channel 1/channel 2 efficiency curve, v in = 5.0 v, f sw = 600 khz, fpwm mode 0 10 20 30 40 50 60 70 80 90 100 01234 efficien c y (%) i out (a) f sw =1.0mhz f sw = 600khz f sw = 300khz 10899-005 figure 7. channel 1/channel 2 efficiency curve, v in = 12 v, v out = 1.8 v, fpwm mode 0 10 20 30 40 50 60 70 80 90 100 00 . 11 1 0 efficiency (%) i out (a) v out =1.2v, fpwm v out = 1.2v, auto pwm/psm v out =1.8v, fpwm v out = 1.8v, auto pwm/psm v out =3.3v, fpwm v out = 3.3v, auto pwm/psm 10899-006 figure 8. channel 1/channel 2 efficiency curve, v in = 12 v, f sw = 600 khz, fpwm and automatic pwm/psm modes 0 10 20 30 40 50 60 70 80 90 100 0 0.2 0.4 0.6 0.8 1.0 1.2 efficien c y (%) i out (a) v out =1.2v v out =1.5v v out =1.8v v out =2.5v v out =3.3v v out =5.0v 10899-007 figure 9. channel 3/channel 4 efficiency curve, v in = 12 v, f sw = 600 khz, fpwm mode 0 10 20 30 40 50 60 70 80 90 100 0 0.2 0.4 0.6 0.8 1.0 1.2 efficien c y (%) i out (a) v out =1.2v v out =1.5v v out =1.8v v out =2.5v v out =3.3v 10899-008 figure 10. channel 3/channel 4 efficiency curve, v in = 5.0 v, f sw = 600 khz, fpwm mode
ADP5050 data sheet rev. 0 | page 14 of 60 0 10 20 30 40 50 60 70 80 90 100 0 0.2 0.4 0.6 0.8 1.0 1.2 efficienc y (%) i out (a) f sw = 1.0mhz f sw = 600khz f sw = 300khz 10899-009 figure 11 . channel 3/channel 4 efficiency curve, v in = 12 v, v out = 1.8 v, fpwm mode 0 10 20 30 40 50 60 70 80 90 100 0 0.1 1 2 efficienc y (%) i out (a) v out = 1 . 2 v , fpwm v out = 1 . 2 v , au t o pwm/psm v out = 1 . 8v , fpwm v out = 1 . 8v , au t o pwm/psm v out = 3.3 v , fpwm v out = 3.3 v , au t o pwm/psm 10899-010 figure 12 . channel 3/channel 4 efficiency curve, v in = 12 v, f sw = 600 khz, fpwm and and automatic pwm/psm modes ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 1 2 3 4 load regul a tion (%) i out (a) 10899-0 1 1 figure 13 . channel 1 load regulation, v in = 12 v, v out = 3.3 v, f sw = 600 khz, fpwm mode ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 4.5 6.0 7.5 9.0 10.5 12.0 13.5 15.0 line regul a tion (%) input vo lt age (v) 10899-012 fig ure 14 . channel 1 line regulation, v out = 3.3 v, i o ut = 4 a, f sw = 600 khz, fpwm mode ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 0.2 0.4 0.6 0.8 1.0 1.2 load regul a tion (%) i out (a) 10899-013 figure 15 . channel 3 load regulation, v in = 12 v, v out = 3.3 v, f sw = 600 khz, fpwm mode ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 4.5 6.0 7.5 9.0 10.5 12.0 13.5 15.0 line regul a tion (%) input vo lt age (v) 10899-014 figure 16 . channel 3 line regulation, v out = 3.3 v, i o ut = 1 a, f sw = 600 khz, fpwm mode
data sheet ADP5050 rev. 0 | page 15 of 60 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 ?50 ?20 10 40 70 100 130 feedback vo lt age accurac y (%) temper a ture (c) 10899-015 figure 17 . 0.8 v feedback voltage accuracy vs. temperature for channel 1, adjustable output model ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 0 5 10 15 20 25 30 35 output vo lt age error (%) vid code 10899-016 v i d 1 v i d 2 v i d 3 v i d 4 figure 18 . output voltage error vs. vid code, adjustable output model 550 600 650 700 750 800 850 ?50 ?20 10 40 70 100 130 frequenc y (khz) temper a ture (c) 10899-017 figure 19 . frequency vs. temperature, v in = 12 v 3.0 3.5 4.0 4.5 5.0 5.5 6.0 ?50 0 25 ?25 50 75 125 100 150 quiescent current (ma) temper a ture (c) 10899-018 figure 20 . quescient current vs. temperature (includes pvin1, pvin2, pvin3, and pvin 4) 15 25 35 45 55 65 75 shutdown current (a) temper a ture (c) ?50 0 25 ?25 50 75 125 100 150 v in = 4.5v v in = 7.0v v in = 12v v in = 15v 10899-019 figure 21 . shutdown current vs. temperature (en1, en2, en3, en4, and en5 low) 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 ?50 ?20 10 40 70 100 130 uvlo threshold (v) temper a ture (c) r i s i n g f a l l i n g 10899-020 figure 22 . uvlo threshold vs. temperature
ADP5050 data sheet rev. 0 | page 16 of 60 0 1 2 3 4 5 6 7 4 6 8 10 12 14 16 current limit (a) input vo lt age (v) r il i m = 2 2 k? r il i m = o p e n r il i m = 4 7 k? 10899-021 figure 23 . channel 1/ channel 2 current limit vs. input voltage 0 20 40 60 80 100 120 140 160 180 200 ?50 ?20 10 40 70 100 130 minimum on time (ns) temper a ture (c) c h 1 / c h 2 c h 3 / c h 4 10899-022 figure 24 . minimum on time vs. temperature 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 output vo lt age (v) input vo lt age (v) i out = 1 m a i out = 1 0 m a i out = 5 0 m a i out = 1 0 0 m a i out = 1 5 0 m a i out = 2 0 0 m a 10899-023 figure 25 . channel 5 (ldo regulator) line regulation over output load 0.01 0.1 1 10 100 10 100 1k 10k 100k noise (v/hz) frequency (hz) v out = 1.2v v out = 1.8v v out = 3.3v v out = 2.5v 10899-024 figure 26 . channel 5 ( ldo regulator ) o utput noise spectrum, v in = 5 v, c out = 1 f, i out = 10 ma 0 20 40 60 80 100 120 140 160 180 1 10 100 rms noise (v) i out (ma) v out = 1.2v v out = 1.8v v out = 3.3v v out = 2.5v 10899-025 figure 27 . channel 5 (ldo regulator) output noise vs. output load, v in = 5 v, c out = 1 f ?120 ?100 ?80 ?60 ?40 ?20 0 10 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) i out = 1ma i out = 10ma i out = 50ma i out = 100ma i out = 150ma i out = 200ma 10899-026 figure 28 . channel 5 (ldo regulator) psrr over output load, v in = 5 v, v out = 3.3 v, c out = 1 f
data sheet ADP5050 rev. 0 | page 17 of 60 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) pvin5 = 4.0v; i out = 1ma pvin5 = 3.6v, i out = 1ma pvin5 = 4.0v, i out = 100ma pvin5 = 3.6v, i out = 100ma pvin5 = 4.0v, i out = 200ma pvin5 = 3.6v, i out = 200ma 10899-027 figure 29 . channel 5 (ldo regulator) psrr over various loads and dropout voltages, v out = 3.3 v, c out = 1 f ch1 5.00v ch2 10.0m v b w m1.00s a ch1 7.40v 2 1 v out sw 10899-028 figure 30 . steady state waveform at h eavy load, v in = 12 v, v out = 3.3 v, i out = 3 a, f sw = 600 khz, l = 4.7 h, c out = 47 f 2, fpwm mode 10899-029 ch1 5.00v ch2 50.0m v b w m100s a ch1 11.0mv 2 1 v out sw figure 31 . steady state waveform at light load, v in = 12 v, v out = 3.3 v, i out = 30 ma, f sw = 600 khz, l = 4.7 h, c out = 47 f 2, automatic pwm/psm mode ch1 50.0m v b w ch4 2.00a ? m100s a ch1 ?22.0mv 1 4 v out i out 10899-030 figure 32 . channel 1/channel 2 load transient, 1 a to 4 a, v in = 12 v, v out = 3.3 v, f sw = 600 khz, l = 2.2 h, c out = 47 f 2 ch3 2.00a ? b w ch4 2.00a ? b w ch2 100mv b w m100s a ch2 ?56.0mv 2 4 v out i out2 i out1 10899-031 figure 33 . load transient, chann el 1/channel 2 parallel output, 0 a to 6 a, v in = 12 v, v out = 3.3 v, f sw = 600 khz, l = 4.7 h, c out = 47 f 4 ch1 500m v b w ch2 5.00v ch3 5.00 v b w ch4 2.00a ? m1.00ms a ch1 650mv 1 3 2 4 v out i out en pwrgd 10899-032 figure 34 . channel 1/channel 2 soft start with 4 a resistance load, v in = 12 v, v out = 1.2 v, f sw = 600 khz, l = 1 h, c out = 47 f 2
ADP5050 data sheet rev. 0 | page 18 of 60 ch3 1.00v b w ch1 10.0v b w ch4 1.00a ? b w ch2 5.00v b w m400s a ch2 2.80v 1 4 2 3 10899-033 v in v out en i out figure 35 . startup with precharged output, v in = 12 v, v out = 3.3 v ch3 5.00v b w ch1 500mv b w ch4 5.00a ? b w ch2 5.00v b w m10.0ms a ch1 650mv 1 4 2 3 10899-034 v out i out en pwrgd figure 36 . channel 1/channel 2 shutdown with active output discharge, v in = 12 v, v out = 1.2 v, f sw = 600 khz, l = 1 h, c out = 47 f 2 ch1 500mv b w ch4 5.00a ? ch2 10.00v b w m10.0ms a ch1 970mv 1 4 2 10899-135 v out i out sw figure 37 . short - circuit protection entry, v in = 12 v, v out = 1.2 v, f sw = 600 khz, l = 1 h, c out = 47 f 2 ch1 500mv b w ch4 5.00a ? b w ch2 10.0v b w m10.0ms a ch1 970mv 1 4 2 10899-136 v out i out sw figure 38 . short - circuit protection recovery, v in = 1 2 v, v out = 1.2 v, f sw = 600 khz, l = 1 h, c out = 47 f 2 ch2 200mv b w m200s a ch2 1.21v 2 10899-137 v out figure 39 . channel 1 dynamic voltage scaling (dvs) from 1.1 v to 1.3 v, 62.5 s interval, v in = 12 v, i o ut = 4 a, f sw = 600 khz, l = 1 h, c out = 47 f 2 ch2 200mv b w m200s a ch2 1.18v 2 10899-138 v out figur e 40 . channel 1 dynamic voltage scaling (dvs) from 1.3 v to 1.1 v, 62.5 s interval, v in = 12 v, i o ut = 4 a, f sw = 600 khz, l = 1 h, c out = 47 f 2
data sheet ADP5050 rev. 0 | page 19 of 60 theory of operation the ADP5050 is a micropower management unit that combin es four high performance buck regulators with a 200 ma low dropout (ldo) regulator in a 48 - lead lfcsp package to meet demanding performance and board space requirements. the device enables direct connect ion to high input voltage s up to 15 v with no pre - regulators to make application s simple r and more efficient. buck regulator operationa l modes pwm mode in pulse - width modulation (pwm) mode, the buck regulators in the ADP5050 operate at a fixed frequency; this frequency is set by an internal oscillator that is programmed by the rt pin. at the start of each oscillator cycle, the high - side mosfet turns on and sends a positive voltage across t he inductor. the inductor current increases until the current - sense signal exceeds the peak inductor current threshold that turns off the high - side mosfet; this threshold is set by the error amplifier output. during the high - side mosfet off time, the induc tor current decreases through the low - side mosfet until the next oscillator clock pulse starts a new cycle. the buck regulators in the ADP5050 regulate the output voltage by adjusting the peak in ductor current threshold. psm mode to achieve higher efficiency, the buck regulators in the ADP5050 smoothly transition to variable frequency power save mode (psm) operation when the output load falls below the psm current threshold. when the output voltage falls below regulation, the buck regulator enters pwm mode for a few oscillator cycles until the voltage increases to within regulation. during the idle time between bursts, the mosfet turns of f, and the output capacitor supplies all the output current. the psm comparator monitors the internal compensation node, which represents the peak inductor current information. the average psm current threshold depends on the input voltage (v in ), the outpu t voltage (v out ), the inductor, and the output capacitor. because the output voltage occasionally falls below regulation and then recovers, the output voltage ripple in psm operation is larger than the ripple in the forced pwm mode of operation under light load conditions. forced pwm and automatic pwm/psm modes the buck regulators can be configured to always operate in pwm mode using the sync/mode pin and the i 2 c interface. in forced pwm (fpwm) mode, the regulator continues to operate at a fixed frequency e ven when the output current is below the pwm/psm threshold. in pwm mode, efficiency is lower compared to psm mode under light load conditions. the low - side mosfet remains on when the inductor current falls to less than 0 a, causing the ADP5050 to enter continuous conduction mode (ccm). t he buck regulator s can be configured to operate in automatic pwm /psm mode using t he sync/mode pin and the i 2 c interface . in automatic pwm /psm mode , the buck regul ators operate in either pwm mode or psm mode , depending on the output current. when the average output current falls below the pwm/psm threshold, the buck regulator enter s psm mode operation ; in psm mode , the regulator operates with a reduced switching fre quency to maintain high efficiency. the low - side mosfet turns off when the output current reaches 0 a , causing the regulator to operate in discontinuous mode (dcm). the user can alternate between forced pwm (fpwm) mode and auto matic pwm/psm mode during ope ration. the flexible configuration capability during operation of the device enables efficient power management. when a logic high level is applied to the sync/mode pin (or when sync/mode is configured as a clock input or output), the operational mode of e ach channel is set by the psmx_on bit in register 6. a value of 0 for the psmx_on bit configures the channel for forced pwm mode; a value of 1 configures the channel for automatic pwm/psm mode. when a logic low level is applied to the sync/mode pin , the o perational mode of all four buck regulators is automatic pwm/psm mode, and the settings of the psmx_on bits in r egister 6 are ignored. table 8 describes the function of the sync/mode pin in setting the operational mode of the device. table 8 . configuring the mode of operation using the sync/mode pin sync/mode pin mode of operation for each channel h igh specified by the psmx_on bit setting in r egister 6 (0 = forced pwm mode; 1 = automatic pwm/psm mode) clock i nput/ o utput specified by the psmx_on bit setting in r egister 6 (0 = forced pwm mode; 1 = automatic pwm/psm mode) low automatic pwm/psm mode (psmx_on bit setting s in r egister 6 are i gnore d ) for example, with the sync/mode pin high, write 1 to the psm 4_on bit in register 6 to configure automatic pwm/psm mode operation for channel 4, and write 0 to the psm1_on, psm2_on, and psm3_on bits to configure forced pwm mode for channel 1, channel 2, and channel 3.
ADP5050 data sheet rev. 0 | page 20 of 60 adjustable and fixed output voltages the ADP5050 provides adjustable and fixed output voltage settings via the i 2 c interface or factory fuse. for the adjustable output settings, use an external resistor divider to set the desired output voltage via the feedback reference voltage ( 0.8 v for channel 1 to channel 4, and 0.5 v for channel 5) . for the fixed output settings, the feedback resistor divider is built into t he ADP5050 , an d the feedback pin (fbx) must be tied directly to the output. each buck regulator channel can be programmed for a specific output voltage range using the vid x bits in register 2 to register 4. table 9 lists the fixed o utput voltage ranges configured by the vid x bits. table 9 . fixed output voltage range s set by the vid x b its channel fixed output voltage range set by the vid x b its c hannel 1 0.85 v to 1.6 v in 25 mv step s c hannel 2 3.3 v to 5.0 v in 3 00 mv or 2 00 mv step s c hannel 3 1.2 v to 1.8 v in 100 mv step s c hannel 4 2.5 v to 5.5 v in 100 mv step s the output range can also be programmed by factory fuse. if a different output voltage range is required, contact your local analog devices, inc ., sales or distribution representative. dynamic voltage scal ing (dvs) the ADP5050 provides a dynamic voltage scaling (dvs) function for channel 1 and channel 4; these outputs can be programmed i n real time via the i 2 c interface (register 5, dvs_cfg). the dvs_cfg register is used to enable dvs and to set the step interval during the transition (see table 28). it is recommended that the user enable the dvs function before setting the output voltage for channel 1 or channel 4 . (the out - put voltage for channel 1 is set using the vid1 bits in register 2; the output voltage for channel 4 is set using the vid4 bits in register 4.) if dvs is enabled after the vid value is set, the output voltage changes rapidly to the next target voltage, which can result in problems such as a pwrgd failure or ovp and ocp events. figure 41 shows the dynamic voltage scaling function. output new vid code old vid code old vid new vid vidx vid for ch1 or ch4 dvsx_intval setting 25mv for ch1 (100mv for ch4) 10899-035 figure 41 . dynamic voltage scaling during the dvs transition period, the regulator is forced into pwm mode operation, and ovp latch - off, scp latch - off, and hiccup protection are masked. internal regulators (vreg and vdd) the internal vre g regulator in the ADP5050 provides a stable 5.1 v power supply for the bias voltage of the mosfet drivers. the internal vdd regulator in the ADP5050 provides a stable 3.3 v power supply for internal control circuits. connect a 1.0 f ceramic capacitor between vreg and ground, and connect another 1.0 f ceramic capacitor between vdd and ground. the internal vreg and vdd regulator s are ac tive as long as pvin1 is available. the internal vreg regulator can provide a total load of 95 ma including the mosfet driving current, and it can be used as an always alive 5.1 v power supply for a small system current demand. the current - limit circuit i s included in the vreg regulator to protect the circuit when the part is heavily loaded. t he vdd regulator is for internal circuit use and is not recom - mended for other purposes. separate supply appl ications the ADP5050 supports separate input voltages for the four buck regulators. this means that the input voltages for the four buck regulators can be connected to different supply voltages. the pvin1 voltage provides the power supply for the inter nal regulators and the control circuitry. therefore, if the user plans to use separate supply voltages for the buck regulators, the pvin1 voltage must be above the uvlo threshold before the other channels begin to operate. precision enabling can be used to monitor the pvin1 voltage and to delay the startup of the outputs to ensure that pvin1 is high enough to support the outputs in regulation. for more information, see the precision enabling section. the ADP5050 supp orts cascading supply operation for the four buck regulators. as shown in figure 42 , pvin2, pvin3, and pvin4 are powered from the channel 1 output. in this config - uration, the channel 1 output voltage must be higher than the uvlo threshold for pvin2 , pvin3, and pvin4. pvin1 buck 1 buck 2 v out1 pvin2 to pvin4 v out2 to v out4 v in 10899-036 figure 42 . cascading supply application
data sheet ADP5050 rev. 0 | page 21 of 60 low- side device selectio n the buck regulators in channel 1 and channel 2 integrate 4 a high - side power mosfets and low - side mosfet drivers. the n- channel mosfets selected for use with the ADP5050 must be able to work with the synchronized buck regulators. in general, a low r dson n- channel mosfet can be used to achieve higher efficiency; dual mosfets in one package (for both channel 1 and channel 2) are recommended to save space on the pcb. for more information, see the low - side power device selection secti on. bootstrap circuitry each buck regulator in the ADP5050 has an integrated bootstrap regulator. the bootstrap regulator requires a 0.1 f ceramic capac - itor (x5r or x7r) between the bstx and sw x pins to provide the gate drive voltage for the high - side mosfet. active output discha rge switch each buck regulator in the ADP5050 integrates a discharge switch from the switching node to groun d. this switch is turned on when its associated regulator is disabled, which helps to discharge the output capacitor quickly. the typical value of the discharge switch is 250 ? for channel 1 to channel 4. the discharge switch function can be enabled or disabled for each channel by factory fuse or by using the i 2 c interface ( register 6, opt_cfg) . precision enabling the ADP5050 has an enable control pin for each regulator, including the ldo regulator. the enable control pin (enx) features a precision enable circuit with a 0.8 v reference voltage. when the voltage at the enx pin is greater than 0.8 v, the regulato r is enabled. when the voltage at the enx pin falls below 0.72 5 v, the regulator is disabled. an internal 1 m? pull - down resistor prevents errors if the enx pin is left floating. the precision enable threshold voltage allows easy sequencing of channels within the part, as well as sequencing between the ADP5050 and other input/output supplies. the enx pin can also be used as a programmable uvlo input using a resist or divider (see figure 43 ). for more information, see the programming the uvlo input section. 0.8v deglitch timer interna l enable enx r1 r2 1m? input/output volt age ADP5050 10899-037 figure 43 . precision enable diagram for one channel in addition to the enx pins, the i 2 c interface (register 1, pctrl) can also be used to enable and disable each channel. the on/o ff status of a channel is controlled by the i 2 c enable bit for the channel (chx_on) and the external hardware enable pin for the channel (logical and). the default value of the i 2 c enable bit (chx_on = 1) specifies that the channel enable is controlled by the external hardware enable pin. pulling the external enx pin low resets the channel and forces the corresponding chx_on bit to the default value, 1, to support another startup when the external enx pin is pulled high again. oscillator the switching frequ ency (f sw ) of the ADP5050 can be set to a value from 250 khz to 1.4 mhz by connecting a resistor from the rt pin to ground. the value of the rt resistor can be calculated as follows: r rt (k?) = [ 14,822/ f sw (khz)] 1.081 figure 44 shows the typical relationship between the switching frequency (f sw ) and the rt resistor. the adjustable frequency allows users to make decisions based on the trade - off between efficien cy and solution size . 1.6m 1.4m 1.2m 1.0m 800k frequenc y (hz) 600k 400k 200k 0 0 20 40 rt resis t or (k?) 60 80 10899-044 figure 44 . switching frequency vs. rt resistor for channel 1 and channel 3, the frequency can be set to half the master switching frequency set by the rt pin. this setting is configured using register 8 (bi t 7 for channel 3, and bit 6 for channel 1). if the master switching frequency is less than 250 khz, this halving of the frequency for channel 1 or channel 3 is not recommended.
ADP5050 data sheet rev. 0 | page 22 of 60 phase shift by default, the phase shift between channel 1 and channel 2 and between channel 3 and channel 4 is 180 (see figure 45 ). this value provides the benefits of out - of - phase operation by reduc - ing the input ripple current and lowering the ground noise. ch2 ch1 (? f sw optional) ch4 sw 180 phase shift 0 reference 90 phase shift 270 phase shift 0, 90,180, or 270 adjustable ch3 (? f sw optional) 10899-040 figure 45 . phase shift diagram, four buck regulators for channel 2 to channel 4, the phase shift with respect to channel 1 can be set to 0?, 90?, 180?, or 270? using register 8, sw_cfg (see figure 46 ). when parallel operation of channel 1 and channel 2 is configured, the switching frequency of channel 2 is locked to a 180? phase shift with respect to channel 1. ch3 10.0v b w ch1 10.0v b w ch4 10.0v b w ch2 10.0v b w m400ns a ch1 7.40v 1 2 3 4 10899-146 sw1 sw2 sw3 sw4 figure 46 . i 2 c configurable 90? p hase s hift waveforms, four b uck regulators synch ronization input/out put t he switching frequency of the ADP5050 can be synchronized to an external clock with a frequency range from 250 khz to 1.4 mhz . the ADP5050 automatically detects the presence of an external clock applied to the sync/mode pin , and the switching frequency transitions smoothly to the frequency of the external clock. when the external clock signal stops, the device au tomatically switches back to the internal clock and continues to operate. note that the internal switching frequency set by the rt pin must be programmed to a value that is close to the external clock value for successful synchronization; the suggested frequency differ - ence is less than 15% in typical applications. the sync/mode pin can be configured as a synchronization clock output by factory fuse or via the i 2 c interface (register 10, hiccup_cfg). a positive clock pulse with a 50% duty cycle is gen erated at the sync/mode pin with a frequency equal to the internal switching frequency set by the rt pin. there is a short delay time (approximately 15% of t sw ) from the generated synchronization clock to the channel 1 switching node. figure 47 shows two ADP5050 devices configured for frequency synchronization mode : one ADP5050 device is configured as the clock output to synchronize another ADP5050 device. it is recommended that a 100 k pull - up resistor be us ed to prevent logic errors when the sync/mode pin is left floating. ADP5050 100k? vreg sync/mode sync/mode ADP5050 10899-039 figure 47 . two ADP5050 devices configured for synchronization mode in the configuration shown in figure 47 , the phase shift between channel 1 of the fir st ADP5050 device and channel 1 of the second ADP5050 device is 0? (see figure 48). ch3 5.00v b w ch1 2.00v b w ch2 5.00v b w m400ns a ch1 560mv 1 2 3 10899-148 sw1 at first ADP5050 sw1 at second ADP5050 sync-out at first ADP5050 figure 48 . waveforms of two ADP5050 devices operating in synchronization mode
data sheet ADP5050 rev. 0 | page 23 of 60 soft start the buck regulators in the ADP5050 include soft start circuitry that ramps the output voltage in a controlled manner during startup, thereby limiting the inrush current. the soft start time is typically f ixed at 2 m s for each buck regulator when the ss12 and ss34 pin s are tied to vreg. to set the soft start time to a value of 2 ms, 4 ms, or 8 ms, connect a resistor divider from the ss12 or ss34 pin to the vreg pin and ground (see figu re 49 ). this configuration may be required to accommodate a specific start - up sequence or an application with a large output capacitor. leve l detec t or and decoder vreg t op resis t or bot t om resis t or ss12 or ss34 ADP5050 10899-041 figu re 49 . level detector circuit for soft start the ss12 pin can be used to program the soft start time and parallel operation for c hannel 1 and c hannel 2 . the ss34 pin can be used to program the soft start time for c hannel 3 and c hannel 4. table 10 provides the values of the resistors needed to set the sof t start time . table 10 . soft s tart time set by the ss12 and ss34 p in s soft start time soft start time r top (k?) r bot (k?) channel 1 channel 2 channel 3 channel 4 0 n/a 2 ms 2 ms 2 ms 2 ms 100 600 2 ms parallel 2 ms 4 ms 200 500 2 ms 8 ms 2 ms 8 ms 300 400 4 ms 2 ms 4 ms 2 ms 400 300 4 ms 4 ms 4 ms 4 ms 500 200 8 ms 2 ms 4 ms 8 ms 600 100 8 ms parallel 8 ms 2 ms n/a 0 8 ms 8 ms 8 ms 8 ms parallel operation the adp 5050 supports two - phase parallel operation of channel 1 and channel 2 to provide a single output with up to 8 a of current. to configure channel 1 and channel 2 as a two - phase single output in parallel operation, do the following (see figure 50): ? use the ss12 pin to select parallel operation as specified in table 10. ? leave the comp2 pin open. ? us e the fb1 pin to set the output voltage. ? connect the fb2 pin to ground ( fb2 is ig nored). ? connect the en2 pin to ground (en 2 is ig nored). channel 1 buck regulator (4a) channel 2 buck regulator (4a) fb1 pvin1 v out (up to 8a) v in en1 en2 comp1 ss12 sw1 l1 fb2 sw2 l2 pvin2 comp2 vreg 10899-042 figure 50 . parallel operation for channel 1 and channel 2 when channel 1 and channel 2 are operated in the parallel configuration, configure the channels as follows: ? set the input voltages and current - limit settings for channel 1 and channel 2 to the same values. ? operate both channels in forced pwm mode. bits pertaining to channel 2 in the configuration registers cannot be used. these bits include ch2_on in register 1, vid2 in register 3, ovp2_ on and scp2_on in register 7, phase2 in register 8, and pwrg2 in register 13. c urrent balance in parallel configuration is well regulated by the internal control loop. figure 51 shows the typical current balance matching in the parall el output configuration. 0 1 2 3 4 5 6 0 2 4 6 8 10 channe l current (a) t ot al output load (a) ch 1 ch 2 i d ea l 10899-151 figure 51 . current balance in parallel output configuration, v in = 12 v, v out = 1.2 v, f sw = 6 00 khz, fpwm mode startup with prechar ged output the buck regulators in the ADP5050 include a precharged start - up feature to protect the low - side fets from damage during startup. if the output voltage is precharged before the regulator is turned on, the regulator prevents reverse inductor current which discharges the output capacitor until the internal soft start reference voltage exceeds the precharged voltage on the feedback (fbx) pin.
ADP5050 data sheet rev. 0 | page 24 of 60 current - limit protection the buck regulators in the adp50 50 include peak current - limit protection circuitry to limit the amount of positive current flowing through the high - side mosfet. the peak current limit on the power switch limits the amount of current that can flow from the input to the output. the progra mmable current - limit threshold feature allows for the use of small size inductors for low current applications. t o configure the current - limit threshold for channel 1 , c onnect a resistor from the dl1 pin to ground ; to configure the current - limit threshold for channel 2 , connect another resistor from the dl2 pin to ground. table 11 lists the peak current - limit threshold settings for channel 1 and channel 2. table 11 . peak current - limit threshold s ettings for channel 1 and channel 2 r ilim1 or r ilim2 typical peak current - limit t hreshold floating 4 .4 a 47 k? 2 .63 a 22 k? 6.4 4 a the buck regulators in the ADP5050 include negative curren t - limit protection circuitry to limit certain amounts of negative current flowing through the low - side mosfet. frequency foldback the buck regulators in the ADP5050 include frequency fold - back to prevent output current runaway when a hard short occurs on the output. frequency foldback is implemented as follows: ? if the voltage at the fbx pin falls below half the target output voltage, the switching frequency is reduced by half. ? if the voltage at t he fbx pin falls again to below one - fourth the target output voltage, the switching frequency is reduced to half its current value, that is, to one - fourth of f sw . the reduced switching frequency allows more time for the inductor current to decrease, but al so increases the ripple cur - rent during peak current regulation. this results in a reduction in average current and prevents output current runaway. pulse skip mode under maximum duty cycle under maximum duty cycle conditions, frequency foldback maintain s the output in regulation. if the maximum duty cycle is reached for example, when the input voltage decreases the pwm modulator skips every other pwm pulse, resulting in a switching frequency foldback of one - half. if the duty cycle increases further, the pw m modulator skips two of every three pwm pulses, resulting in a switching frequency foldback to one - third of the switching frequency. frequency foldback increases the effective maximum duty cycle, thereby decreasing the dropout voltage between the input an d output voltages. hiccup protection the buck regulators in the ADP5050 include a hiccup mode for overcurrent protection (ocp) . when the peak induc tor current reaches the current - limit threshol d, the high - side mosfet turns off and the low - side mosfet turns on until the next cycle. when hiccup mode is active, the overcurrent fault counter is incremented. if the overcurrent fault counter reaches 15 and overflows (indicating a short - circuit conditi on), both the high - side and low - side mosfets are turned off. the buck regulator remains in hiccup mode for a period equal to seven soft start cycles and then attempts to restart from soft start. if the short - circuit fault has cleared, the regulator resumes normal operation; otherwise, it reenters hiccup mode after the soft start. hiccup protection is masked during the initial soft start cycle to enable startup of the buck regulator under heavy load conditions. note that careful design and proper component s election are required to ensure that the buck regulator recovers from hiccup mode under heavy loads. the hiccupx_off bits in register 10 can be used to disable hiccup protection for each buck regulator. when hiccup protection is disabled, the frequency fol dback feature is still available for overcurrent protection. latch - off protection the buck regulator s in the ADP5050 ha ve an optional latch - off mode to protect the device from serious problems su ch as short - circuit and overvoltage conditions. latch - off mode can be enabled via the i 2 c interface or by factory fuse . short - circuit latch - off mode short - circuit latch - off mode is enabled by factory fuse or by writing a 1 to the scpx_on bit in register 7 , lch_cfg. when short - circuit latch - off mode is enabled and the protection circuit detects an overcurrent status after a soft start, the buck regulator enters hiccup mode and attempts to restart. if seven continuous re start attempts are made and the regulat or remains in the fault condition, the regulator is shut down. this shutdown (latch - off) condition is cleared only by reenabling the channel or by resetting the channel power supply. figure 52 shows the short - circuit l atch - off de tection function. output voltage time latch-off chx_lch latch off this regulator short circuit detected by counter overflow pwrgd 7 t ss scp latch-off function enabled after 7 restart attempts write 1 to chx_lch bit attempt to restart 10899-045 figure 52 . short - circuit latch - off detection
data sheet ADP5050 rev. 0 | page 25 of 60 the short - circuit latch - off status can be read from register 12, lch _status . to clear th e status bit, write a 1 to the bit (pro - vided that the fault no lon ger persists). t h e status bit is latched until a 1 is written to the bit or the part is reset by the internal vdd power - on reset signal. note that short - circuit latch - off mode does not work if hiccup protection is disabled. overvoltage latch - off mode overv oltage latch - off mode is enabled by factory fuse or by writing a 1 t o the ovpx_on bit in register 7, lch_cfg. the overvoltage latch - off threshold is 124% of the nominal output voltage level. when the output voltage exceeds this threshold, the protection ci rcuit detects the overvoltage status and the regu - lator shuts down. this shutdown (latch - off) condition is cleared only by reenabling the channel or by resetting the channel power supply. figure 53 shows the overvoltage latch - off dete ction function. output voltage time latch off this regulator latch-off chx_lch write 1 to chx_lch bit 124% nominal output 100% nominal output 10899-046 chx on figure 53 . overvoltage latch - off detection the overvoltage latch - off status can be read from register 12, lch _status . to clear th e status bit, write a 1 to the bit (pro - vided that the fault no longer persists). t h e status bit is latched until a 1 is written to the bit or the part is reset by the internal vdd power - on reset signal. undervoltage lockout (uvlo) undervoltage lockout circuitry monitors the input voltage level of each buck regulator in the ADP5050 . if any input voltage (pvinx pin) falls below 3.78 v (typical), the corresponding channel is turned off. after the input voltage rises above 4.2 v (typical), the soft start period is initiated, and the corresponding channel is enabled when the enx pin is high. note that a uvlo condition on channel 1 (pvin 1 pin) has a higher priority than a uvlo condition on other channel s, which means that the pvin1 supply must be available before other channels can be operated. power - good function the ADP5050 includes an open - drain power - good output (pwrgd pin) that becomes active high when the selected buck regulators are operating normally. by default, the pwrgd pin monitors the output voltage on channel 1. other channels can be configured to control the pwrgd pin when the ADP5050 is ordered (see table 56). the power - good status of each channel (pwrgx bit) can be read back via the i 2 c interface (register 13, status_rd). a value of 1 for the pwrgx bit indicates that the regulated out - put voltage of the buck regulator is above 90.5% (typical) of its nomin al output. when the regulated output voltage of the buck regulator falls below 87.2% (typical) of its nominal output for a delay time greater than approximately 50 s, the pwrgx bit is set to 0. the output of the pwrgd pin is the logical and of the interna l unmasked pwrgx signal s. an i nternal pwrgx signal must be high for a va lidation time of 1 ms before the pwrgd pin goes high; if one pwrgx signal fails, the pwrgd pin goes low with no delay . the channels that control the pwrgd pin (channel 1 to channel 4 ) are specified by factory fuse or by setting the appro - priate bits in register 11 (pwrgd_mask) via the i 2 c interface. interrupt function the ADP5050 provides an interrupt output (nint pin) for fau lt conditions. during normal operation, the nint pin is pulled high (an external pull - up resistor should be used). when a fault condition occurs, the ADP5050 pulls the nint pin low to alert the i 2 c host processor that a fault condition has occurred. s ix interrupt sources can trigger the nint pin. by default, no interrupt sources are configured. to select one or more interrupt sources to trigger the nint pin, set the appropriate bits to 1 in regist er 15, int_mask (see table 48). when the nint pin is triggered, one or more bits in register 14 (bits[5:0]) are set to 1. the fault condition that triggered the nint pin can be read from register 1 4 , int_status (see table 12) . table 12 . fault conditions for device interrupt (register 14) interrupt description temp_int junction temperature has exceeded the con - figured threshold (selected in register 9) lvin_int pvin1 v oltage has fallen below the configur ed threshold ( selected in register 9 ) pwrg4_int power - g ood f ailure d etected on channel 4 pwrg3_int power - g ood f ailure d etected on channel 3 pwrg2_int power - g ood f ailure d etected on channel 2 pwrg1_int power - g ood f ail ure d etected on channel 1 to clear an interrupt, write a 1 to the appropriate bit in register 14 (int_status), take all enx pins low, or reset the part using the internal vdd power - on reset signal. reading the interrupt or writing a 0 to the bit does not clear the interrupt.
ADP5050 data sheet rev. 0 | page 26 of 60 thermal shutdown if the ADP5050 junction temperature exceeds 150 c, the thermal shutdown circuit turns off the ic except for the internal linear regulator s . extreme junction temperatures can be the result of high current operation, poor circuit board design, or high ambient temperature. a 15 c hysteresis is included so that the ADP5050 does not return to operation af ter thermal shutdown until the on - chip temperature falls below 135 c. when the part exits ther - mal shutdown, a soft start is initiated for each enabled channel. the thermal shutdown status can be read via the i 2 c interface (register 12, lch_status). when t hermal shutdown is detected, the tsd_lch bit (bit 4) is set to 1. to clear the status bit, write a 1 to the bit ( provided that the fault no longer persists ) . the status bit is latched until a 1 is written to the bit or the part is reset by the internal vdd power - on reset signal. overheat detection in addition to thermal shutdown protection , the ADP5050 provides an overheat warning function, which compares the junction temperature with the specifie d overheat threshold: 105 , 115 , or 125 . the overheat threshold is configured in register 9, t h _ cfg . unlike thermal shutdown, the overheat detection function send s a warning signal but does not shut down the part . when the junction temperature exceeds th e overheat threshold, the status bit temp_int in register 14 is set to 1 . t h e status bit is latched until a 1 is written to the bit , all enx pins are taken low, or the part is reset by the internal vdd power - on reset signal. the overheat detection functio n can be used to send a warning signal to the host processor. after the host processor detect s the overheat warning signal, the processor can take action to prepare for a possible impending thermal shutdown. figure 54 shows the overh eat warning function. junction temperature time temp_int (heat status) overheat condition detected normal temperature 115c (adjustable) 10899-047 figure 54 . overheat w arning f unction low input voltage de tection in addition to undervoltage lockout (uvlo), the ADP5050 provides a low input v oltage detection circuit to monitor pvin1; this circuit compares the input voltage with the specified voltage threshold. the voltage threshold can be set from 4.2 v to 11.2 v in steps of 0.5 v using register 9, th_cfg. unlike uvlo shut - down, the low input voltage detection function sends a warning signal but does not shut down the part. when the pvin1 input voltage falls below the threshold, the status bit lvin_int in register 14 is set to 1. the status bit is latched until a 1 is written to the bit , all en x pins are taken low, or the part is reset by the internal vdd power - on reset signal. the low input voltage detection function can be used to send a warning signal to the host processor. after the host processor detect s the low input voltage warning signal , the processor can take action to prepare for a possible impending uvlo shutdown. figure 55 shows the low input voltage warning function. input voltage on pvin1 time lvin_int (lvin status) low input voltage condition detected 12v input voltage 10.7v (adjustable) 10899-048 figure 55 . low i nput v oltage w arning f unction ( v in = 12 v) ldo regu lator the ADP5050 integrates a general - purpose ldo regulator with low quiescent current and low dropout voltage . the ldo regu - lator provides up to 200 ma of output current. the ldo regulator oper ates with an input voltage of 1.7 v to 5.5 v. the wide supply range makes the regulator suitable for cascading configurations where the ldo supply voltage is provided from one of the buck regulators. the ldo output voltage is set using an external resistor divider (see figure 56). ldo fb5 vout5 en5 pvin5 c1 1f r a r b c2 1f 1.7v to 5.5v 10899-049 figure 56 . 200 ma ldo regulator the ldo regulator provides a high power supply rejection ratio (psrr), low output noise, and excellent line and load transient response using small 1 f ceramic input and output capacitors.
data sheet ADP5050 rev. 0 | page 27 of 60 i 2 c interface the ADP5050 includes an i 2 c - compatible serial interface for control of the power management blocks and for readback of system status (s ee figure 57 ). the i 2 c interface operates at clock frequencies of up to 400 khz. i 2 c register scl sda level shifter vddio vdd vddio uvlo_vddio trim data scp/ovp vddio vdd vdd vdd vddio 10899-051 figure 57 . i 2 c interface block diagram note that the ADP5050 does not respond to general calls. the ADP5050 accepts multiple masters, but if the device is in read mode, access is limited to one master until the data transmission is complete d. the i 2 c serial interface can be used to access the internal registers of the ADP5050 . for complete information about the ADP5050 re gisters, see the register map section. sda and scl pins the ADP5050 has two dedicated i 2 c interface pins, sda and scl. sda is an open - drain line for rece iving and transmitting data . scl is an input line for receiving the clock signal. pull up t hese pins to the vddio supply using external resistors . serial data is transferred on the rising edge of scl. the read data is generated at the sda pin in read mode. i 2 c addresses the default 7 - bit i 2 c chip address for the ADP5050 is 0x48 (1001000 in binary). a different i 2 c address can be configured using the optional a0 pin, which can replace the power - go od functionality on pin 20. (for information about obtaining an ADP5050 model with pin 20 functioning as the a0 pin, contact your local analog devices sales or distribution representative.) the a 0 pin allows the use of two ADP5050 devices on the same i 2 c communication bus. figure 58 shows two ADP5050 devices configure d with different i 2 c addresses using the a0 pin . 10899-050 scl vddio i 2 c inter f ace i 2 c address = 0x48 i 2 c address = 0x49 a0 sda scl vddio a0 vreg sda figure 58 . two ADP5050 devices configured with different i 2 c address es ( a0 function repla ces pwrgd function on p in 20 ) s elf - clear register bit s register 12 and register 14 are status registers that contain self - clear register bit s. these bit are cleared automatically when a 1 is written to the status bit. therefore, it is not necessary to writ e a 0 to the status bit to clear it.
ADP5050 data sheet rev. 0 | page 28 of 60 i 2 c interface timing d iagrams figure 59 shows the timing diagram for the i 2 c write operation. figure 60 shows the timing diagram for the i 2 c read operation. the suba ddress is used to select one of the user registers in the ADP5050 . the ADP5050 sends data to and from the register specified by the su baddress. scl chip address sda a0 a1 a2 a3 a4 a5 a6 a0 a1 a2 a3 a4 a5 a6 a7 0 0 0 0 1 0 0 1 d0 d1 d2 d3 d4 d5 d6 d7 subaddress write data ack by slave write start ack by slave ack by slave r/w stop notes 1. maximum scl frequency is 400khz. 2. no response to general calls. output by processor output by ADP5050 10899-052 figure 59 . i 2 c write to register scl chip address sda a0 a1 a2 a3 a4 a5 a6 a0 a1 a2 a3 a4 a5 a6 a7 0 0 0 0 1 0 0 1 1 0 0 0 1 0 0 1 d0 d1 d2 d3 d4 d5 d6 d7 subaddress chip address read data notes 1. maximum scl frequency is 400khz. 2. no response to general calls. output by processor output by ADP5050 ack by slave write start ack by slave read ack by slave no ack by master to stop reading r/w a0 a1 a2 a3 a4 a5 a6 r/w stop 10899-053 figure 60 . i 2 c read from register
data sheet ADP5050 rev. 0 | page 29 of 60 applications information adisimpower design tool the ADP5050 is supported by the adisimpower ? design tool set. adisimpower is a collection of tools that produce complete power designs optimized for a specific design goal. the tools enable the user to generate a full schematic and bill of materials and to calculate performance in minutes. adisimpower can optimize designs for cost, area, efficiency, and part count while taking into consideration the operating conditions and limitations of the ic and all real external components. the adisimpower tool can be found at www.analog.com/adisimpower ; the user can request an unpopulated board through the tool. programming the adjustable output voltage the output voltage of the ADP5050 is externally set by a resistive voltage divider from the output voltage to the fbx pin. to limit the degradation of the output voltage accuracy due to feedback bias current, ensure that the bottom resistor in the divider is not too largea value of less than 50 k is recommended. the equation for the output voltage setting is v out = v ref (1 + ( r top / r bot )) where: v out is the output voltage. v ref is the feedback reference voltage: 0.8 v for channel 1 to channel 4 and 0.5 v for channel 5. r top is the feedback resistor from v out to fb. r bot is the feedback resistor from fb to ground. no resistor divider is required in the fixed output options. each channel has vidx bits to program the output voltage for a specific range (see table 9). if a different fixed output voltage (default vid code) is required, contact your local analog devices sales or distribution representative. voltage conversion limitations for a given input voltage, upper and lower limitations on the output voltage exist due to the minimum on time and the minimum off time. the minimum output voltage for a given input voltage and switching frequency is limited by the minimum on time. the minimum on time for channel 1 and channel 2 is 117 ns (typical); the minimum on time for channel 3 and channel 4 is 90 ns (typical). the minimum on time increases at higher junction temperatures. note that in forced pwm mode, channel 1 and channel 2 can potentially exceed the nominal output voltage when the mini- mum on time limit is exceeded. careful switching frequency selection is required to avoid this problem. the minimum output voltage in continuous conduction mode (ccm) for a given input voltage and switching frequency can be calculated using the following equation: v out_min = v in t min_on f sw ? ( r dson1 ? r dson2 ) i out_min t min_on f sw ? ( r dson2 + r l ) i out_min (1) where: v out_min is the minimum output voltage. t min_on is the minimum on time. f sw is the switching frequency. r dson1 is the on resistance of the high-side mosfet. r dson2 is the on resistance of the low-side mosfet. i out_min is the minimum output current. r l is the resistance of the output inductor. the maximum output voltage for a given input voltage and switching frequency is limited by the minimum off time and the maximum duty cycle. note that the frequency foldback feature helps to increase the effective maximum duty cycle by lowering the switching frequency, thereby decreasing the dropout voltage between the input and output voltages (see the frequency foldback section). the maximum output voltage for a given input voltage and switch- ing frequency can be calculated using the following equation: v out_max = v in (1 ? t min_off f sw ) ? (r dson1 ? r dson2 ) i out_max (1 ? t min_off f sw ) ? ( r dson2 + r l ) i out_max (2) where: v out_max is the maximum output voltage. t min_off is the minimum off time. f sw is the switching frequency. r dson1 is the on resistance of the high-side mosfet. r dson2 is the on resistance of the low-side mosfet. i out_max is the maximum output current. r l is the resistance of the output inductor. as shown in equation 1 and equation 2, reducing the switching frequency eases the minimum on time and off time limitations. current-limit setting the ADP5050 has three selectable current-limit thresholds for channel 1 and channel 2. make sure that the selected current- limit value is larger than the peak current of the inductor, i peak . see table 11 for the current-limit configuration for channel 1 and channel 2.
ADP5050 data sheet rev. 0 | page 30 of 60 soft start setting the buck regulators in the ADP5050 include soft start circuitry that ramps the output voltage in a controlled manner during startup, thereby limiting the inrush current. to set the soft start time to a value of 2 ms, 4 ms, or 8 ms, connect a resistor divider from the ss12 or ss34 pin to the vreg pin and ground (see the soft start section). induc tor selection the inductor value is determined by the switchi ng frequency, input voltage, output voltage, and inductor ripple current. using a small inductor value yields faster transient response but degrades efficiency due to the larger inductor ripple c urrent. using a large inductor value yields a smaller ripple current and better efficiency but results in slower transient response. thus, a trade - off must be made between transient response and efficiency. as a guideline, the inductor ripple current, i l , is typically set to a value from 30% to 40% of the maximum load current. the inductor value can be calculated using the following equation: l = [( v in ? v out ) d ]/( i l f sw ) where: v in is the input voltage. v out is the output voltage. d is the duty cycle ( d = v out / v in ) . i l is the inductor ripple current. f sw is the switching frequency. the ADP5050 has internal slope compensation in the current loop to prevent subharmonic oscillations when the d uty cycle is greater than 50%. the peak inductor current is calculated using the following equation: i peak = i out + ( i l /2) the saturation current of the inductor must be larger than the peak inductor current. for ferrite core inductors with a fast satura tion characteristic, make sure that the saturation current rating of the inductor is higher than the current - limit threshold of the buck regulator to prevent the inductor from becoming saturated. the rms current of the inductor can be calculated using the following equation: 12 2 2 l out rms i i i ? + = shielded ferrite core materials are recommended for low core loss and low emi. table 13 lists recommended inductors. table 13 . recommended inductors vendor part n o. value (h) i sat (a) i rms (a) dcr (m?) size (mm) coilcraft xfl4020 - 102 1.0 5.4 11 10.8 4 4 xfl4020 - 222 2.2 3.7 8.0 21.35 4 4 xfl4020 - 332 3.3 2.9 5.2 34.8 4 4 xfl4020 - 472 4.7 2.7 5.0 52.2 4 4 x a l40 3 0 - 68 2 6 . 8 3.6 3.9 67.4 4 4 x a l40 4 0 - 1 03 10 2.8 2.8 84 4 4 xal6030 - 102 1.0 23 18 5.62 6 6 xal6030 - 222 2.2 15.9 10 12.7 6 6 xal6030 - 332 3.3 12.2 8.0 19.92 6 6 xal6060 - 472 4.7 10.5 11 14. 4 6 6 xal6060 - 682 6.8 9.2 9.0 18.9 6 6 toko fdv0530 - 1r0 1.0 11.2 9.1 9.4 6.2 5.8 f dv0530 - 2r2 2.2 7.1 7.0 17.3 6.2 5.8 fdv0530 - 3r3 3.3 5.5 5.3 29.6 6.2 5.8 fdv0530 - 4r7 4.7 4.6 4.2 46.6 6.2 5.8 output capacitor sel ection the selected output capacitor affects both the output voltage ripple and the loop dynamics of the regulator. for example, during load step transients on the output, when the load is suddenly increased, the output capacitor supplies the load until the control loop can ramp up the inductor current, causing an undershoot of the output voltage. t he output capacitanc e required to meet the undershoot ( voltage droop ) requirement can be calculated using the following equation: ( ) uv out out in step uv uv out v v v l i k c _ 2 _ 2 ? ? ? = where: k uv is a factor ( typically set to 2 ) . i step is the load step. v out_uv is the allowable undershoot on the output voltage. another example of the effect of the output capacitor on the loop dynamics of the regulator is when the load is suddenly removed from the output and the energy stored in t he inductor rushes into the output capacitor, causing an overshoot of the output voltage . the output capacitance required to meet the overshoot require - ment can be calculated using the following equation: ( ) 2 2 2 _ out out_ov out step ov ov out v v v l i k c ? ? + ? = where: k ov is a factor ( typi cally set to 2 ) . i step is the load step. v out_ o v is the allowable overshoot on the output voltage.
data sheet ADP5050 rev. 0 | page 31 of 60 the output voltage ripple is determined by the esr of the output capacitor and its capacitance value. use the following equation s to select a capacitor that can meet the output ripple requirements: ripple out sw l ripple out v f i c _ _ 8 ? ? = l ripple out esr i v r ? ? = _ where: i l is the inductor ripple current. f sw is the switching frequency. v out_ripple is the allowable output voltage ripple. r esr is the equivalent series resistance of the outpu t capacitor. select the largest output capacitance given by c out_uv , c out_ov , and c out_ripple to meet both load transient and output ripple requirements . the voltage rating of the selected output capacitor must be grea ter than the output voltage. the minim um rms cu rrent rating of the output capacitor is determined by the following equation : 12 _ l rms c i i out ? = input capacitor sele ction the input decoupling capacitor attenuates high frequency noise on the input and acts as an energy reservoir. use a ceram ic capac - itor and place it close to the pvinx pin. the loop composed of the input capacitor, the high - side nfet, and the low - side nfet must be kept as small as possible. the voltage rating of the input capacitor must be greater than the maximum input volta ge. make sure that the rms current rating of the input capacitor is larger than the following equation: ( ) d d i i out rms c in ? = 1 _ where d is the duty cycle ( d = v out / v in ) . low - side power device se lection channel 1 and channel 2 include integrated low - side mos fet drivers, which can drive low - side n - chan ne l mosf e ts (n f e ts ). the selection of the low - side n - channel mosfet affects the performance of the buck regulator . the selected mosfet must meet the following requirements: ? drain - to - source voltage (v ds ) must be h igher than 1.2 v in . ? drain current (i d ) must be greater than 1.2 i limit_max , where i limit_max is the selected maximum current - limit threshold. ? the selected mosfet can be fully turned on at v gs = 4.5 v. ? total gate charge (qg at v gs = 4.5 v) must be less than 20 nc. lower qg characteristics provide higher efficiency. when the high - side mosfet is turned off, the low - side mosfet supplies the inductor current. for low duty cycle applications, the low - side mosfet supplies the current for most of the period. to achieve higher efficiency, it is important to select a mosfet with low on resistance. the power conduction loss for the low - side mosfet can be calculated using the following equation: p fet_low = i out 2 r dson (1 ? d ) w here : r dson is the on resistance of the low - side mos fet . d is the duty cycle ( d = v out / v in ) . table 14 lists recommended dual mosfets for various current - limit settings. ensure that the mos fet can handle thermal dissipation d ue to power loss. table 14 . recommended dual mosfets vendor part no. v ds (v) i d (a) r dson (m?) qg (nc) size (mm) ir irfhm8363 30 10 20.4 6.7 3 3 irlhs6276 20 3.4 45 3.1 2 2 fairchild fdma1024 20 5.0 54 5.2 2 2 fdmb3900 2 5 7.0 33 11 3 2 fdmb3800 30 4.8 51 4 3 2 fdc6401 20 3.0 70 3.3 3 3 vishay si7228 dn 30 23 25 4.1 3 3 si7232 dn 20 25 16.4 12 3 3 si7904bdn 20 6 30 9 3 3 si5906du 30 6 40 8 3 2 si5908dc 20 5.9 40 5 3 2 sia906edj 20 4.5 46 3.5 2 2 aos aon7804 30 22 26 7.5 3 3 aon7826 20 22 26 6 3 3 ao6800 30 3.4 70 4.7 3 3 aon2800 20 4.5 47 4.1 2 2 programming the uvlo input the precision enable input can be used to program the uvlo threshold of the input voltage, as shown in figure 43 . to l im it the degradation of the input voltage accuracy due to the internal 1 m? pull - down resistor tolerance, ensure that the bottom resistor in the divider is not too large a value of less than 50 k? is recomm ended. the precision turn - on threshold is 0.8 v . th e resistive voltage divider for the programmable v in start - up voltage is calculated as follows: v in_startup = (0.8 na + (0.8 v/ r bot_en )) ( r top_en + r bot_en ) where: r top_en is the resistor from v in to en. r bot_en is the resistor from en to ground .
ADP5050 data sheet rev. 0 | page 32 of 60 compensation compone nts design for the peak current - mode control architecture , the power stage can be simplified as a voltage controlled current source that supplies current to the output capacitor and load resistor. the simplified loop is composed of one domain pole and a zero contributed by the output capacitor esr. the control - to - output transfer function is s hown in the following equations: ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? + = = p z vi comp out vd f s f s r a s v s v s g 2 1 2 1 ) ( ) ( ) ( out esr z c r f = 2 1 ( ) out esr p c r r f + = 2 1 w here : a vi = 10 a/v for channel 1 or channel 2, and 3.33 a/v for channel 3 or channel 4. r is the load resistance . r esr is the equivalent series resistance of the output capacitor . c out is the output capacitance . the ADP5050 uses a transconductance amplifier as the error amplifier to compensate the system. figure 61 shows the sim - plified peak current - mode control small signal circuit. r esr r + ? g m r c c cp c out c c r top r bot ? + a vi v out v comp v out 10899-054 figure 61 . simplified peak current - mode control small signal circuit the compensation components, r c and c c , contribute a zero; r c and the optional c cp contribute an optional pole. the closed - loop transfer equation is as follows: ) ( 1 1 ) ( s g s c c c c r s s c r c c g r r r s t vd cp c cp c c c c cp c m top bot bot v ? ? ? ? ? ? ? ? + + + + ? + = the following guidelines show how to select the compensation components r c , c c , and c cp for ceramic output capacitor applications. 1. determine the cross frequency (f c ). generally, f c is between f sw /12 and f sw /6. 2. calculate r c using the following eq uation: vi m c out out c a g f c v r = v 8 . 0 2 3. place the compensation zero at the domain pole (f p ). calculate c c using the following equation : ( ) c out esr c r c r r c + = 4. c cp is optional. it can be used to cancel the zero caused by the esr of the output capacitor. calculate c cp using the following equation : c out esr cp r c r c = power dissipation the total power dissipation in the ADP5050 simplifies to p d = p buck1 + p buck2 + p buck3 + p buck4 + p ldo buck regulator power dissipation the power dissipation (p loss ) for each buck regulator includes power switch conduction losses (p cond ), switching losses (p sw ), and transition losses (p tran ). other sources of power dissipation exist, but these sources are generally less s ignificant at the high output currents of the application thermal limit. use t he following equation to estimate the power dissipation of the buck regulator : p loss = p cond + p sw + p tran p ower s witch c onduction l oss (p cond ) p ower switch conduction losses are caused by the flow of output current through both the high - side and low - side power switches, each of which has its own internal on resistance ( r dson ) . use the following equation to estimate t he power switch conduction loss: p cond = ( r ds on_hs d + r dson_ l s (1 ? d )) i out 2 w here : r dson _hs is the on resistance of the high - side m osf e t. r ds on _l s is the on resistance of the low - side mosfet. d is the duty cycle ( d = v out / v in ) .
data sheet ADP5050 rev. 0 | page 33 of 60 switching loss (p sw ) switching losses are associated with the current drawn by the driver to turn the power devices on and off at the switching frequency. each time a power device gate is turned on or off, the driver transfers a charge from the input supply to the gate, and then from the gate to ground. use the following equation to estimate the switching loss: p sw = ( c gate_hs + c gate_ls ) v in 2 f sw where: c gate_hs is the gate capacitance of the high-side mosfet. c gate_ls is the gate capacitance of the low-side mosfet. f sw is the switching frequency. transition loss (p tran ) transition losses occur because the high-side mosfet cannot turn on or off instantaneously. during a switch node transition, the mosfet provides all the inductor current. the source-to- drain voltage of the mosfet is half the input voltage, resulting in power loss. transition losses increase with both load and input voltage and occur twice for each switching cycle. use the following equation to estimate the transition loss: p tran = 0.5 v in i out ( t r + t f ) f sw where: t r is the rise time of the switch node. t f is the fall time of the switch node. thermal shutdown channel 1 and channel 2 store the value of the inductor current only during the on time of the internal high-side mosfet. therefore, a small amount of power (as well as a small amount of input rms current) is dissipated inside the ADP5050 , which reduces thermal constraints. however, when channel 1 and channel 2 are operating under maximum load with high ambient temperature and high duty cycle, the input rms current can become very large and cause the junction temperature to exceed the maximum junction tem- perature of 125c. if the junction temperature exceeds 150c, the regulator enters thermal shutdown and recovers when the junction temperature falls below 135c. ldo regulator power dissipation the power dissipation of the ldo regulator is given by the following equation: p ldo = [( v in ? v out ) i out ] + ( v in i gnd ) where: v in and v out are the input and output voltages of the ldo regulator. i out is the load current of the ldo regulator. i gnd is the ground current of the ldo regulator. power dissipation due to the ground current is small in the ADP5050 and can be ignored. junction temperature the junction temperature of the die is the sum of the ambient temperature of the environment and the temperature rise of the package due to power dissipation, as shown in the following equation: t j = t a + t r where: t j is the junction temperature. t a is the ambient temperature. t r is the rise in temperature of the package due to power dissipation. the rise in temperature of the package is directly proportional to the power dissipation in the package. the proportionality constant for this relationship is the thermal resistance from the junction of the die to the ambient temperature, as shown in the following equation: t r = ja p d where: t r is the rise in temperature of the package. ja is the thermal resistance from the junction of the die to the ambient temperature of the package (see table 6). p d is the power dissipation in the package. an important factor to consider is that the thermal resistance value is based on a 4-layer, 4 inch 3 inch pcb with 2.5 oz. of copper, as specified in the jedec standard, whereas real-world applications may use pcbs with different dimensions and a different number of layers. it is important to maximize the amount of copper used to remove heat from the device. copper exposed to air dissipates heat better than copper used in the inner layers. connect the exposed pad to the ground plane with several vias.
ADP5050 data sheet rev. 0 | page 34 of 60 design example this section provides an example of the step - by - step design procedures and the external components required for channel 1. table 15 list s the design requirements for this example . table 15. example design requirement s f or channel 1 parameter specification i nput v oltage v pvin1 = 12 v 5% output voltage v out1 = 1.2 v o utput current i out1 = 4 a output ripple v out1_ripple = 12 mv in ccm m ode load transient 5% at 20% to 80% l oad t ransient, 1 a/ s al though this example shows step - by - step design procedure s for channel 1, the procedure s appl y to all other buck regulator channels (c hannel 2 to c hannel 4 ). settin g the switching freq uency the first step is to de termine the switching frequency for the ADP5050 design. in general, higher switching frequenc ies produce a smaller solution size due to the low er component value s required , whereas lower switching frequenc ies result in higher conversion efficiency due to low er switching loss es. the switching frequency of the ADP5050 can be set to a value f rom 250 khz to 1.4 mhz by connecting a resistor from the rt pin to ground . the selected resistor allows the user to make decisions based on the trade - off between efficiency and solution size. (for more information, see the oscillator section.) however, the highest supported switching frequency must be assessed by checking the voltage conversion limitations enforced by the minimum on time and the minimum off time (see the voltage conversion l imitations section) . in this design example, a switching frequency of 600 khz is used to achieve a good combination of small solution size and high conversion efficiency. to set the switching frequency to 600 khz, use the following equation to calculate t he resistor value, r rt : r rt (k?) = [14,822/ f sw (khz)] 1.081 therefore, select standard resistor r rt = 31.6 k. setting the output v oltage select a 10 k bottom resistor (r bot ) and then calculate the top feedback resistor using the following equation: r bot = r top ( v ref /( v out ? v ref ) ) where: v ref is 0.8 v for channel 1. v out is the output voltage. to set the output voltage to 1.2 v, choose the following resistor values : r top = 4.99 k, r bot = 10 k . setting the current limit for 4 a output current operation, the typical peak current l imit is 6 .44 a. for this example, choose r ilim1 = 22 k? (see table 11 ). for more information, see the current - limit protection section. selecting the inductor the peak - to - peak inductor ripple current, i l , is set to 3 5 % of the maximum output current. use the following equation to estimate the value of the inductor: l = [( v in ? v out ) d ]/( i l f sw ) where: v in = 12 v. v out = 1.2 v. d is the duty cycle ( d = v out / v in = 0.1). i l = 35% 4 a = 1.4 a. f sw = 600 khz. the resulting value for l is 1.28 h. the closest standard inductor value is 1.5 h; therefore, the inductor ripple current, i l , is 1.2 a. the peak inductor current is calculated using the following equation: i peak = i ou t + ( i l /2) the calculated peak current for the inductor is 4.6 a. the rms current of the inductor can be calculated using the following equation: 12 2 2 l out rms i i i ? + = the rms current of the inductor is approximately 4.02 a. therefore, an inductor with a minimum rms current rating of 4.02 a and a minimum saturation current rating of 4.6 a is required. however, to pr event the inductor from reaching its saturation point in current - limit condition s, it is recommended that the inductor saturation current be higher than the maximum peak current limit, typical ly 7.48 a, for reliable operation. based on these requirements and recommendations, the toko fdv0530 - 1r5, with a dcr of 13.5 m, is selected for this design.
data sheet ADP5050 rev. 0 | page 35 of 60 selecting the output capacitor the output capacitor must meet the output voltage ripple and load transient requirement s . to meet the output voltage ripple requirement, use the following equation s to calculate the es r and capacit ance : ripple out sw l ripple out v f i c _ _ 8 ? ? = l ripple out esr i v r ? ? = _ the calculated capacitance , c out_ripple , is 20.8 f, and the calculated r esr is 10 m . to meet the 5% overshoot and undershoot requirement s, use the following equation s to calculate the cap acitance: ( ) uv out out in step uv uv out v v v l i k c _ 2 _ 2 ? ? ? = ( ) 2 2 2 _ out out_ov out step ov ov out v v v l i k c ? ? + ? = for estimation purposes, use k ov = k uv = 2 ; therefore, c out_ov = 117 f and c out_ u v = 13.3 f. the esr of the output capacitor must be less than 13.3 m, and the output capacit ance must be greater t han 117 f. it is recommended that three ceramic capacitor s be used ( 47 f, x5r, 6.3 v ), such as the grm21br60j476me15 from murata with an esr of 2 m . selecting the low - s ide mosfet a low r dson n - channel mosfet must be selected for high efficiency solution s. the mosfet breakdown voltage (v ds ) must be greater than 1.2 v in , and the drain current must be greater than 1.2 i limit _max . it is recommended that a 20 v, dual n - channel mosfet such as the si7232 dn from vishay be used for both channel 1 and channel 2 . the r ds on of the si7232 dn at 4.5 v driver voltage is 16.4 m, and the total gate charge is 12 nc. designing the compensation network for better load transient and stability performance, set the cross frequency, f c , to f sw /10. in this example, f sw is set to 600 khz; therefore, f c is set to 60 khz. for the 1.2 v ou tput rail, the 47 f ceramic output capacitor has a derated value of 40 f . ? = = k 4 . 14 a/v 10 s 470 v 8 . 0 khz 60 f 40 3 v 2 . 1 2 c r ( ) nf 51 . 2 k 4 . 14 f 40 3 001 . 0 3 . 0 = ? ? + ? = c c pf 3 . 8 k 4 . 14 f 40 3 001 . 0 = ? ? = cp c choose standard components : r c = 15 k and c c = 2.7 n f. c cp is optional . figure 62 shows the b ode plot for the 1.2 v output rail. the cross frequency is 62 khz, and the phase margin is 58. figure 63 shows the load transient waveform. 100 ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 120 ?180 ?150 ?120 ?90 ?60 ?30 0 30 60 90 1k 10k 100k 1m magnitude (db) phase (degrees) frequency (hz) cross frequency: 62khz phase margin: 58 10899-161 figure 62 . bode p lot for 1.2 v o utput ch1 50.0m v b w &+$? b w m200s a ch4 2.32a 1 4 v out i out 10899-162 figure 63 . 0.8 a to 3.2 a load transient for 1.2 v o utput selecting the soft start time the soft start feature allows the output voltage to ramp up in a controlled manner, eliminating output voltage overshoo t during soft start and limiting the in rush current. the ss12 pin can be used to program a soft start time of 2 ms, 4 ms , or 8 ms and can also be used to configure parallel opera - tion of c hannel 1 and c hannel 2. for more information, see the soft start section and table 10. selecting the input capacitor for the input capacitor, select a ceramic capacitor with a mini - mum value of 10 f; place the input capacitor close to the pvin1 pin. in this example, one 10 f, x5r, 25 v ceramic capacitor is recommended.
ADP5050 data sheet rev. 0 | page 36 of 60 recommended external components table 16 lists t he r ecommended external components for 4 a applications use d with channel 1 and channel 2 of the ADP5050 . table 17 lists t he r ecommended external components for 1.2 a applications use d with channel 3 and channel 4. table 16. recommended external components for typical 4 a ap plications, c hannel 1 and c hannel 2 (1% output ripple, 7.5% t olerance at ~60% step transient) f sw (khz) i out (a) v in (v) v out (v) l (h) c out (f) r top (k ?) r bot (k ?) r c (k ?) c c (pf) dual fet 300 4 12 (or 5) 1.2 3.3 2 100 1 4.99 10 10 4700 si 7232dn 12 (or 5) 1.5 3.3 2 100 1 8.87 10.2 10 4700 si7232dn 12 (or 5) 1.8 3.3 3 47 2 12.7 10.2 6.81 4700 si7232dn 12 (or 5) 2.5 4.7 3 47 2 21.5 10.2 10 4700 si7232dn 12 (or 5) 3.3 6.8 3 47 2 31.6 10.2 10 4700 si7232dn 12 5.0 6.8 47 3 52.3 10 4.7 4 700 si7232dn 600 4 12 (or 5) 1.2 1.5 2 47 2 4.99 10 10 2700 si7232dn 12 (or 5) 1.5 1.5 2 47 2 8.87 10.2 10 2700 si7232dn 12 (or 5) 1.8 2.2 2 47 2 12.7 10.2 10 2700 si7232dn 12 (or 5) 2.5 2.2 2 47 2 21.5 10.2 10 2700 si7232dn 12 (or 5) 3.3 3.3 2 47 2 31.6 10.2 15 2700 si7232dn 12 5.0 3.3 47 3 52.3 10 10 2700 si7232dn 1000 4 5 1.2 1.0 2 47 2 4.99 10 15 1500 si7232dn 5 1.5 1.0 2 47 2 8.87 10.2 15 1500 si7232dn 12 (or 5) 1.8 1.0 47 2 12.7 10.2 10 1500 si7232dn 12 (or 5) 2.5 1.5 47 2 21.5 10.2 10 1500 si7232dn 12 (or 5) 3.3 1.5 47 2 31.6 10.2 10 1500 si7232dn 12 5.0 2.2 47 3 52.3 10 15 1500 si7232dn 1 100 f capacitor : murata grm31cr60j107me39 ( 6.3 v, x5r, 1206). 2 47 f capacitor : murata grm21br60j476me15 ( 6.3 v, x5r, 0805). 3 47 f capacitor : murata grm31cr61a476me15 ( 10 v, x5r, 1206). table 17. recommended external components for typical 1.2 a applications , c hannel 3 and c hannel 4 (1% output ripple, 7.5% t olerance at ~60% step transient) f sw (khz) i out (a) v in (v) v out (v) l (h) c out (f) r top (k ?) r bot (k ?) r c (k ?) c c (pf) 300 1.2 12 (or 5) 1.2 10 2 22 1 4.99 10 6.81 4700 12 (or 5) 1.5 10 2 22 1 8.87 10.2 6.81 4700 12 (or 5) 1.8 1 5 2 22 1 12.7 10.2 6.81 4700 12 (or 5) 2.5 1 5 2 22 1 21.5 10.2 6.81 4700 12 (or 5) 3.3 22 2 22 1 31.6 10.2 6.81 4700 12 5.0 22 22 2 52.3 10 6.81 4700 600 1.2 12 (or 5) 1.2 4.7 22 1 4.99 10 6.81 2700 12 (or 5) 1.5 6.8 22 1 8.87 10.2 6.81 2700 12 (or 5) 1.8 6.8 22 1 12.7 10.2 6.81 2700 12 (or 5) 2.5 10 22 1 21.5 10.2 6.81 2700 12 (or 5) 3.3 1 0 22 1 31.6 10.2 6.81 2700 12 5.0 10 22 2 52.3 10 6.81 2700 1000 1.2 5 1.2 2.2 22 1 4.99 10 1 0 1 8 00 12 (or 5) 1.5 3.3 22 1 8.87 10.2 1 0 1 8 00 12 (or 5) 1.8 4.7 22 1 12.7 10.2 10 1 8 00 12 (or 5) 2.5 4.7 22 1 21.5 10.2 10 1 8 00 12 (or 5) 3.3 6.8 22 1 3 1.6 10.2 10 1 8 00 12 5.0 6.8 22 2 52.3 10 15 1 8 00 1 22 f capacitor : murata grm188r60j226mea0 ( 6.3 v, x5r, 0603). 2 22 f capacitor : murata grm219r61a226mea0 ( 10 v, x5r, 0805).
data sheet ADP5050 rev. 0 | page 37 of 60 circuit board layout recommendations good circuit board layout is essentia l to obtain the best perfor - mance from the ADP5050 (see figure 65 ). poor layout can affect the regulation and stability of the part, as well as the elect ro - magnetic interference (emi) and electromagnetic compatibility (emc) performance. refer to the following guidelines for a good pcb layout. ? place the input capacitor, inductor, mosfet , output capacitor, and bootstrap capacitor close to the ic. ? use short, thick traces to connect the input capacitors to the pvinx pins, and use dedicated power ground to connect the input and output capacitor grounds to minimize the connection length. ? use several high current vias, if required, to connect pvinx, pgndx, and sw x to other power planes. ? use short, thick traces to connect the inductors to the swx pins and the output capacitors. ? ensure that the high current loop traces are as short and wide as possible. figure 64 shows the high current path. ? maximize the amount of ground metal for the exposed pad, and use as many vias as possible on the component side to improve thermal dissipation. ? use a ground plane with several vias connecting to the com - ponent side ground to further re duce noise interference on sensitive circuit nodes. ? place the decoupling capaci tors close to the vreg and vdd pins. ? place the frequency s etting resistor close to the rt pin. ? place the feedback resist or divider close to the fbx pin . in addition, keep the fb x traces away from the high current traces and the switch node to avoid noise pickup. ? use size 0402 or 0603 resistors and capacitors to achieve the smallest possible footprint solution on boards where space is limited. v in v out pvinx enx gnd bstx swx ADP5050 dlx fbx 10899-055 figure 64 . t ypical circuit with high current traces shown in blue 10899-163 figure 65 . typical pcb layout for the ADP5050
ADP5050 data sheet rev. 0 | page 38 of 60 typical application circuits vreg channel 2 buck regulator (1.2a/2.5a/4a) channel 3 buck regulator (1.2a) oscillator int vreg 100ma q1 q2 l1 l2 5v reg sync/mode rt fb1 bst1 sw1 dl1 pgnd dl2 sw2 bst2 fb2 l3 bst3 sw3 fb3 pgnd3 alert l4 10h 4.7h 4.7h 2.2h sia906edj (46m?) 31.6k? 6.81k? 2.7nf 6.81k? 2.7nf 6.81k? 2.7nf 6.81k? 2.7nf bst4 sw4 fb4 pgnd4 nint vreg pvin1 comp1 en1 pvin2 comp2 en2 pvin3 ss34 comp3 en3 vddio optional i 2 c interface pvin4 comp4 en4 scl sda c2 10f c1 1.0f c4 47f c3 0.1f c5 10f c6 0.1f c9 0.1f c7 47f c8 10f c10 22f c11 10f c12 0.1f c13 22f 12v vout1 vout2 vddio processor 3.3v/2.5a 2.85v/100ma 1.5v/1.2a 4.0v to 4.5v/1.2a (dvs) 1.1v to 1.3v/2.5a (dvs) ddr term. ldo ddr memory rfpa rf transceiver nint vcore i/o vout3 vout4 pwrgd 5v reg exposed pad ss12 vreg c0 1.0f vdd channel 5 200ma ldo regulator fb5 en5 vout5 pvin5 c15 1f 10k? 47k? c14 1f vout5 ADP5050 channel 1 buck regulator (1.2a/2.5a/4a) channel 4 buck regulator (1.2a) vreg optional i 2 c interface scl sda scl sda 10899-056 i 2 c figure 66 . typical femtocell application, 600 khz switching frequency, fixed output model
data sheet ADP5050 rev. 0 | page 39 of 60 vreg channel 2 buck regulator (1.2a/2.5a/4a) channel 3 buck regulator (1.2a) oscillator int vreg 100ma q1 q2 l1 l2 sync/mode rt fb1 bst1 sw1 dl1 pgnd dl2 sw2 bst2 fb2 l3 bst3 sw3 fb3 pgnd3 alert l4 10h 6.8h 2.2h 1.5h bst4 sw4 fb4 pgnd4 nint vreg pvin1 comp1 en1 pvin2 comp2 en2 pvin3 ss34 comp3 en3 vddio optional i 2 c interface pvin4 comp4 en4 scl sda c2 10f c1 1.0f c4 47f c3 0.1f c5 10f c6 0.1f c7 47f c8 10f c9 0.1f c10 22f c11 10f c12 0.1f c13 22f 12v vout1 vout2 fpga 2.5v/4a 1.2v/100ma 1.5v/1.2a 3.3v/1.2a 1.2v/4a ddr term. ldo ddr memory flash memory vcore i/o bank 1 i/o bank 0 i/o bank 2 vout3 vout4 22k? 31.6k? 22k? pwrgd ss12 vreg c0 1.0f vdd channel 5 200ma ldo regulator fb5 en5 vout5 pvin5 c15 1f c14 1f vout5 ADP5050 channel 1 buck regulator (1.2a/2.5a/4a) channel 4 buck regulator (1.2a) c16 47f c17 47f vreg mgts i/o bank 3 auxiliary voltage 10899-057 exposed pad i 2 c si7232dn (16.4m?) 5v reg 5v reg 6.81k? 2.7nf 10k? 2.7nf 10k? 2.7nf 6.81k? 10k? 10.2k? 31.6k? 10.2k? 8.87k? 10.2k? 4.99k? 10k? 21.5k? 14k? 2.7nf figure 67 . typical fpga application, 600 khz switching frequency, adjustable output model
ADP5050 data sheet rev. 0 | page 40 of 60 vreg channel 2 buck regulator (1.2a/2.5a/4a) channel 3 buck regulator (1.2a) oscillator int vreg 100ma q1 q2 l1 1.5h 1.5h 6.8h 10h l2 5v reg sync/mode rt fb1 bst1 sw1 dl1 pgnd dl2 sw2 bst2 fb2 vreg l3 bst3 sw3 fb3 pgnd3 alert l4 bst4 sw4 fb4 pgnd4 nint vreg pvin1 comp1 en1 pvin2 comp2 en2 pvin3 ss34 comp3 en3 vddio pvin4 comp4 en4 scl sda c2 10f 2.7nf 10k? 100k? 600k? 31.6k? 2.7nf 6.81k? 2.7nf 6.81k? c1 1.0f c4 100f c3 0.1f c5 10f c6 0.1f c8 10f c9 0.1f c10 22f c11 10f c12 0.1f c13 22f c14 1f c15 1f 12v vout1 vout3 1.2v/8a 1.5v/1.2a 3.3v/1.2a 2.5v/200ma vout4 22k? 22k? i 2 c optional i 2 c interface pwrgd 5v reg exposed pad ss12 c0 1.0f vdd channel 5 200ma ldo regulator fb5 en5 vout5 vout5 ADP5050 channel 1 buck regulator (1.2a/2.5a/4a) channel 4 buck regulator (1.2a) c16 100f vreg pvin5 4.99k? 10k? 8.87k? 31.6k? 40.2k? 10.2k? 10.2k? 10k? si7232dn (16.4m?) 10899-165 figure 68 . typical channel 1/channel 2 parallel output application, 600 khz switching frequency, adjustable output model
data sheet ADP5050 rev. 0 | page 41 of 60 register map table 18. register map register address register name reg . bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0x00 reserved reserved 1 0x01 pctrl reserved ch5_on ch4_on ch3_on ch2_on ch1_on 2 0x02 vid1 reserved vid1[4:0] 3 0x03 vid23 reserved vid3[2:0] reserved vid2[2:0] 4 0x04 vid4 reserved vid4[4:0] 5 0x05 dvs_cfg reserved dvs4_on dvs4_intval[1:0] re served dvs1_on dvs1_intval[1:0] 6 0x06 opt_cfg dscg4_on dscg3_on dscg2_on dscg1_on psm4_on psm3_on psm2_on psm1_on 7 0x07 lch_cfg ovp4_on ovp3_on ovp2_on ovp1_on scp4_on scp3_on scp2_on scp1_on 8 0x08 sw_cfg freq 3 freq 1 phase4[1:0] phase3[1:0] phase2[1: 0] 9 0x09 th_cfg reserved temp_th[1:0] lvin_th[3:0] 10 0x0a hiccup_cfg sync_out reserved hiccup 4_ off hiccup 3_ off hiccup 2_ off hiccup 1_ off 11 0x0b pwrgd_mask reserved mask_ch4 mask_ch3 mask_ch2 mask_ch1 12 0x0c lch_status reserved tsd_lch ch4_lch ch3 _lch ch2_lch ch1_lch 13 0x0d status_rd reserved pwrg4 pwrg3 pwrg2 pwrg1 14 0x0e int_status reserved temp_int lvin_int pwrg4_ int pwrg3_int pwrg2_ int pwrg1_ int 15 0x0f int_mask reserved mask_temp mask_lvin mask_ pwrg4 mask_ pwrg3 mask_ pwrg2 mask_ pwrg1 16 0x10 reserved reserved 17 0x11 default_set default_set[7:0]
ADP5050 data sheet rev. 0 | page 42 of 60 detail ed register description s this section describes the bit functions of each register used by the ADP5050 . to reset a registe r, the internal vdd power - on reset signals must be l ow, unless otherwise noted. register 1: pctrl (c hannel enable contro l), address 0 x 01 r egister 1 is used to enable and disable the operation of each channel. the on or off status of a channel is controlled by the chx_on bit in this register and the external hardware enable pin for the channel (logical and). the default value of the chx_on bit, 1, means that the channel enable is controlled by the external hardware enable pin. the channel can be disabled or enabled via the i 2 c interface only when the enx pin is high. pulling the enx pin low resets the corresponding chx_on bit to the default value (1) to allow another valid startup when the enx pin is high again. table 19. register 1 bit assignment s bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved ch5_on ch4_on ch3_on ch2_on ch1_on table 20. pctrl register , bit function descriptions bits bit name access description [ 7 :5] reserved r/w reserved. 4 ch5_on r/w 0 = disable channel 5 (en5 pin must be high). 1 = enable channel 5 (default). 3 ch4_on r/w 0 = disable channel 4 (en4 pin must be high). 1 = enable channel 4 (default). 2 ch3_on r/w 0 = disable channel 3 (en3 pin must be high). 1 = enable chan nel 3 (default). 1 ch2_on r/w 0 = disable channel 2 (en2 pin must be high). 1 = enable channel 2 (default). 0 ch1_on r/w 0 = disable channel 1 (en1 pin must be high). 1 = enable channel 1 (default). register 2: vid1 ( vid setting for channel 1 ) , address 0 x 02 r egister 2 is used to set the output voltage for channel 1. table 21. register 2 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved vid1[4:0] table 22. vid1 register , bit func tion descriptions bits bit name access description [ 7 :5] reserved r/w reserved. [4:0] vid1[4:0] r/w these bits set the output voltage for channel 1. the default value is programmed by factory fuse. 00000 = 0.8 v (adjustable). 00001 = 0.85 v. 00010 = 0.875 v. 00011 = 0.9 v. 00111 = 1.0 v. 10011 = 1.3 v. 11011 = 1.5 v. 11110 = 1.575 v. 11111 = 1.6 v.
data sheet ADP5050 rev. 0 | page 4 3 of 60 register 3: vid23 ( vid setting for channel 2 and channel 3 ) , address 0 x 03 r egister 3 is used to set the output voltage for channel 2 and channel 3 . table 23. register 3 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved vid3[2:0] reserved vid2[2:0] table 24. vid23 register , bit function descriptions bits bit name access descri ption 7 reserved r/w reserved. [6:4] vid3[2:0] r/w these bits set the output voltage for channel 3. the default value is programmed by factory fuse. 000 = 0.8 v (adjustable). 001 = 1.2 v. 010 = 1.3 v. 011 = 1.4 v. 100 = 1.5 v. 101 = 1.6 v. 110 = 1.7 v. 111 = 1.8 v. 3 reserved r/w reserved. [2:0] vid2[2:0] r/w these bits set the output voltage for channel 2. the default value is programmed by factory fuse. 000 = 0.8 v (adjustable). 001 = 3. 3 v . 010 = 3.6 v . 011 = 3. 9 v . 100 = 4.2 v . 101 = 4.5 v . 110 = 4.8 v . 111 = 5.0 v . register 4: vid4 (vi d setting for c hannel 4 ) , address 0 x 04 r egister 4 is used to set the output voltage for channel 4 . table 25. register 4 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved vid4[4:0] table 26. vid4 register , bit function descriptions bits bit name access description [ 7 :5] reserved r/w reserved. [4:0] vid4[4:0] r/w these bits set the output voltage for channel 4. the default value is pro grammed by factory fuse. 00000 = 0.8 v (adjustable). 00001 = 2.5 v. 00010 = 2.6 v. 00110 = 3.0 v. 10000 = 4.0 v. 11010 = 5.0 v. 11110 = 5.4 v. 11111 = 5.5 v.
ADP5050 data sheet rev. 0 | page 44 of 60 register 5: dvs_cfg ( dvs configuration fo r channel 1 and channel 4 ) , address 0 x 05 re gister 5 is used to configure dynamic voltage scaling (dvs) for channel 1 and channel 4 (see the dynamic voltage scaling (dvs) section). table 27. register 5 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved dvs4_on dvs4_intval[1:0] reserved dvs1_on dvs1_intval[1:0] table 28. dvs_cfg register , bit function descriptions bits bit name access description 7 reserved r/w reserved. 6 dvs4_on r/w 0 = disable dvs for channel 4 (default). 1 = enable dvs for channel 4. [5:4] dvs4_intval[1:0] r/w these bits configure the dvs interval for channel 4. 0 0 = 62.5 s (default). 01 = 31.2 s. 1 0 = 15.6 s. 11 = 7.8 s. 3 reserved r/w reserved. 2 dvs1_on r/w 0 = disable dvs for channel 1 (default). 1 = enable dvs for channel 1. [1: 0 ] dvs1_intval[1:0] r/w these bits configure the dvs interval for channel 1. 0 0 = 62.5 s (default). 01 = 31.2 s. 1 0 = 15.6 s. 11 = 7.8 s.
data sheet ADP5050 rev. 0 | page 45 of 60 register 6: o pt_cfg ( fpwm/psm mode and output discharge fun ction configuration) , address 0 x 06 register 6 is used to configure the operational mode and the discharge switch setting for channel 1 to channel 4. the psmx_on bit setting for each channel is in effect when th e sync/mode pin is high (or when sync/mode is configured as a clock input or output ). when the sync/mode pin is low, all channels are forced to work in automatic pwm/psm mode, and the psmx_on settings in this register are ignored. the default value for the output discharge function can be programmed by factory fuse (output discharge function enabled or disabled for all four buck regulators). table 29. register 6 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dscg 4_on dscg3_on dscg2_on dscg1_on psm4_on psm3_on psm2_on psm1_on table 30. opt_cfg register , bit function descriptions bits bit name access description 7 dscg4_on r/w the default value is programmed by factory fuse. 0 = disable ou tput discharge function for channel 4. 1 = enable output discharge function for channel 4. 6 dscg3_on r/w the default value is programmed by factory fuse. 0 = disable output discharge function for channel 3. 1 = enable output discharge function for channe l 3. 5 dscg2_on r/w the default value is programmed by factory fuse. 0 = disable output discharge function for channel 2. 1 = enable output discharge function for channel 2. 4 dscg1_on r/w the default value is programmed by factory fuse. 0 = disable outp ut discharge function for channel 1. 1 = enable output discharge function for channel 1. 3 psm4_on r/w this bit is ignored when the sync/mode pin is low. 0 = enable forced pwm mode for channel 4 (default) . 1 = enable automatic pwm/psm mode for channel 4. 2 psm3_on r/w this bit is ignored when the sync/mode pin is low. 0 = enable forced pwm mode for channel 3 (default) . 1 = enable automatic pwm/psm mode for channel 3. 1 psm2_on r/w this bit is ignored when the sync/mode pin is low. 0 = enable forced pwm m ode for channel 2 (default) . 1 = enable automatic pwm/psm mode for channel 2. 0 psm1_on r/w this bit is ignored when the sync/mode pin is low. 0 = enable forced pwm mode for channel 1 (default) . 1 = enable automatic pwm/psm mode for channel 1.
ADP5050 data sheet rev. 0 | page 46 of 60 register 7: lch_cfg (short - circuit latch - off and overvoltage latc h - off configuration), address 0 x 07 register 7 is used to enable and disable the latch - off function for short - circuit protection (scp) and overvoltage protection (ovp) . when the scp or ov p latch - off function is enabled, the chx_lch bit in register 12 is set after an error condition occurs (see the latch - off protection section). the default value for the scp latch - off and ovp latch - off functions can be programmed by factory fuse (scp or ovp latch - off function enabled or disabled for all four buck regulators). table 31. register 7 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ovp4_on ovp3_on ovp2_on ovp1_o n scp4_on scp3_on scp2_on scp1_on table 32. lch_cfg register , bit function descriptions bits bit name access description 7 ovp4_on r/w the default value is programmed by factory fuse. 0 = disable the ovp latch - off function for ch annel 4. 1 = enable the ovp latch - off function for channel 4. 6 ovp3_on r/w the default value is programmed by factory fuse. 0 = disable the ovp latch - off function for channel 3. 1 = enable the ovp latch - off function for channel 3. 5 ovp2_on r/w the defa ult value is programmed by factory fuse. 0 = disable the ovp latch - off function for channel 2. 1 = enable the ovp latch - off function for channel 2. 4 ovp1_on r/w the default value is programmed by factory fuse. 0 = disable the ovp latch - off function for c hannel 1. 1 = enable the ovp latch - off function for channel 1. 3 scp4_on r/w the default value is programmed by factory fuse. 0 = disable the scp latch - off function for channel 4. 1 = enable the scp latch - off function for channel 4. 2 scp3_on r/w the def ault value is programmed by factory fuse. 0 = disable the scp latch - off function for channel 3. 1 = enable the scp latch - off function for channel 3. 1 scp2_on r/w the default value is programmed by factory fuse. 0 = disable the scp latch - off function for channel 2. 1 = enable the scp latch - off function for channel 2. 0 scp1_on r/w the default value is programmed by factory fuse. 0 = disable the scp latch - off function for channel 1. 1 = enable the scp latch - off function for channel 1.
data sheet ADP5050 rev. 0 | page 47 of 60 register 8: sw_cfg ( switching frequency and phase shift conf iguration), address 0 x 08 r egister 8 is used to configure the switching frequency for channel 1 and channel 3 and to configure the phase shift for channel 2, channel 3, and channel 4 with respect to channe l 1 (0?). the default values for the channel 1 and channel 3 switching frequencies can be programmed b y factory fuse . table 33. register 8 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 freq3 freq1 phase4[1:0] pha se3[1:0] phase2[1:0] table 34. sw_cfg register , bit function descriptions bits bit name access description 7 freq3 r/w the default value can be programmed by factory fuse. 0 = switching frequency for channel 3 is the same as the master frequency set by the rt pin. 1 = switching frequency for channel 3 is half the master frequency set by the rt pin. 6 freq1 r/w the default value can be programmed by factory fuse. 0 = switching frequency for channel 1 is the same as the master freq uency set by the rt pin. 1 = switching frequency for channel 1 is half the master frequency set by the rt pin. [5:4] phase4[1:0] r/w these bits configure the phase shift for channel 4 with respect to channel 1 (0). 0 0 = 0 phase shift. 01 = 90 phase shi ft. 1 0 = 180 phase shift (default). 11 = 270 phase shift. [3:2] phase3[1:0] r/w these bits configure the phase shift for channel 3 with respect to channel 1 (0). 0 0 = 0 phase shift (default). 01 = 90 phase shift. 1 0 = 180 phase shift. 11 = 270 phas e shift. [1: 0 ] phase2[1:0] r/w these bits configure the phase shift for channel 2 with respect to channel 1 (0). 0 0 = 0 phase shift. 01 = 90 phase shift. 1 0 = 180 phase shift (default). 11 = 270 phase shift.
ADP5050 data sheet rev. 0 | page 48 of 60 register 9: th_cfg ( temp erature warning and low v in warning threshold co nfiguration), address 0 x 09 r egister 9 is used to configure the junction temperature overheat detection threshold and the low input voltage detection threshold. when these thresholds are enabled, the temp_int and lvin_int status bits in register 14 are set if the thresholds are exceeded. table 35. register 9 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved temp_th[1:0] lvin_th[3:0] table 36. th_cfg register , bit function descriptions bits bit name access description [ 7 :6] reserved r/w reserved. [5:4] temp_th[1:0] r/w these bits set the junction temperature overheat threshold. 00 = temperature warning function disabled (default). 01 = 105c. 10 = 115c. 11 = 125c. [3:0] lvin_th[3:0] r/w these bits set the low input voltage detection threshold. 0000 = 4.2 v (default). 0001 = 4.7 v. 0010 = 5.2 v. 0011 = 5.7 v. 0100 = 6.2 v. 0101 = 6.7 v. 0110 = 7.2 v. 0111 = 7.7 v. 1000 = 8.2 v. 1001 = 8.7 v. 1010 = 9.2 v. 1011 = 9.7 v. 1100 = 10.2 v. 1101 = 10.7 v. 1110 = 11.2 v. 1111 = low input voltage warning function disabled.
data sheet ADP5050 rev. 0 | page 49 of 60 register 10: hiccup_ cfg ( hiccup configura tion), address 0 x 0a register 10 is used to configure the sync/mode pin as a synchronization input or output and to configure hiccup protection for each channel. the default value for hiccup protection can be programmed by factory fuse (hiccup function enab led or disabled for all four buck regulators). table 37. register 10 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sync_out reserved hiccup4_off hiccup3_off hiccup2_off hiccup1_off table 38. hiccup_cfg register , bit function descriptions bits bit name access description 7 sync_out r/w the default value can be programmed by factory fuse. 0 = configure the sync/mode pin as a clock synchronization input if a clock is connected (default). 1 = configure the sync/mode pin as a clock synchronization output. [6:4] reserved r/w reserved. 3 hiccup4_off r/w the default value can be programmed by factory fuse. 0 = enable hiccup protection for channel 4. 1 = disable hiccup protection for channel 4 (s hort - circuit protection is disabled automatically). 2 hiccup3_off r/w the default value can be programmed by factory fuse. 0 = enable hiccup protection for channel 3. 1 = disable hiccup protection for channel 3 (short - circuit protection is disabled automa tically). 1 hiccup2_off r/w the default value can be programmed by factory fuse. 0 = enable hiccup protection for channel 2. 1 = disable hiccup protection for channel 2 (short - circuit protection is disabled automatically). 0 hiccup1_off r/w the default v alue can be programmed by factory fuse. 0 = enable hiccup protection for channel 1. 1 = disable hiccup protection for channel 1 (short - circuit protection is disabled automatically).
ADP5050 data sheet rev. 0 | page 50 of 60 register 11: pwrgd_m ask ( channel mask configurati on for pwrgd pin), a ddress 0 x 0b r egister 11 is used to mask or unmask the power - good status of channel 1 to channel 4; when unmasked, a power - good failure on any of these channels triggers the pwrgd pin. the output of the pwrgd pin represents the logical a nd of all unmasked pwrgd signals; that is, the pwrgd pin is pulled low by any pwrgd signal failure. there is a 1 ms validation delay time before the pwrgd pin goes high. the default value for the power - good mask configuration can be programmed by factory fuse (mask function enabled or disabled for all four buck regulators). table 39. register 11 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved mask_ch4 mask_ch3 mask_ch2 mask_ch1 table 40. pwrgd_mask register , bit function descriptions bits bit name access description [7:4] reserved r/w reserved. 3 mask_ch4 r/w the default value can be programmed by factory fuse. 0 = mask power - good status of channel 4. 1 = output power - good statu s of channel 4 to the pwrgd pin. 2 mask_ch3 r/w the default value can be programmed by factory fuse. 0 = mask power - good status of channel 3. 1 = output power - good status of channel 3 to the pwrgd pin. 1 mask_ch2 r/w the default value can be programmed b y factory fuse. 0 = mask power - good status of channel 2. 1 = output power - good status of channel 2 to the pwrgd pin. 0 mask_ch1 r/w the default value can be programmed by factory fuse. 0 = mask power - good status of channel 1. 1 = output power - good status of channel 1 to the pwrgd pin.
data sheet ADP5050 rev. 0 | page 51 of 60 register 12: lch_sta tus ( latch - off status readback) , address 0 x 0c register 12 contains latched fault flags for thermal shutdown and channel latch - off caused by an ovp or scp condition. latched flags are no t reset when the fault disappears but are cleared only when a 1 is written to the appropriate bit (provided that the fault no l onger persists). table 41. register 12 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r eserved tsd_lch ch4_lch ch3_lch ch2_lch ch1_lch table 42. lch_status register , bit function descriptions bits bit name access description [7:5] reserved r/w reserved. 4 tsd_lch read/ self - clear 0 = no thermal shutdown has occurr ed. 1 = thermal shutdown has occurred. 3 ch4_lch read/ self - clear 0 = no short - circuit or overvoltage latch - off has occurred on channel 4. 1 = short - circuit or overvoltage latch - off has occurred on channel 4. 2 ch3_lch read/ self - clear 0 = no short - circu it or overvoltage latch - off has occurred on channel 3. 1 = short - circuit or overvoltage latch - off has occurred on channel 3. 1 ch2_lch read/ self - clear 0 = no short - circuit or overvoltage latch - off has occurred on channel 2. 1 = short - circuit or overvolta ge latch - off has occurred on channel 2. 0 ch1_lch read/ self - clear 0 = no short - circuit or overvoltage latch - off has occurred on channel 1. 1 = short - circuit or overvoltage latch - off has occurred on channel 1. register 13: status_ rd ( status readback), a ddress 0 x 0d th e read - only r egister 13 indicates the real - time status of the power - g ood signals for channel 1 to channel 4. table 43. register 1 3 bit assignment s bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved pwrg4 pwrg3 p wrg2 pwrg1 table 44. status_rd register , bit function descriptions bits bit name access description [7:4] reserved r reserved. 3 pwrg4 r 0 = channel 4 power - good status is low (default) . 1 = channel 4 power - good status is high . 2 pwrg3 r 0 = channel 3 power - good status is low (default) . 1 = channel 3 power - good status is high . 1 pwrg2 r 0 = channel 2 power - good status is low (default) . 1 = channel 2 power - good status is high . 0 pwrg1 r 0 = channel 1 power - good status is low (d efault) . 1 = channel 1 power - good status is high .
ADP5050 data sheet rev. 0 | page 52 of 60 register 14: int_sta tus ( interrupt status readback), address 0 x 0e register 14 contains the interrupt status for the following events: junction temperature overheat warning, low input voltage wa rn - ing, and power - good signal failure on channel 1 to channel 4. when any of these unmasked events occur, the nint pin is pulled low to indicate a fault condition. (masking of these events is configured in register 15.) to determine the cause of the fault , read this register. latched flags are not reset when the fault dis - appears but are cleared only when a 1 is written to the appropriate bit or when all enx pins = 0. table 45. register 1 4 bit assignment s bit 7 bit 6 bit 5 bit 4 b it 3 bit 2 bit 1 bit 0 reserved temp_int lvin_int pwrg4_int pwrg3_int pwrg2_int pwrg1_int table 46. int_status register , bit function descriptions bits bit name access description [7:6] reserved r/w reserved. 5 temp_int read/ s elf - clear this bit indicates whether the junction temperature threshold has been exceeded. 0 = junction temperature has not exceeded the threshold. 1 = junction temperature has exceeded the threshold. 4 lvin_int read/ self - clear this bit indicates whether the low voltage input threshold has been exceeded. 0 = low voltage input has not fallen below the threshold. 1 = low voltage input has fallen below the threshold. 3 pwrg4_int read/ self - clear the power - good interrupt is masked when the part is initialize d and during a normal shutdown. 0 = no power - good failure has been detected on channel 4. 1 = power - good failure has been detected on channel 4. 2 pwrg3_int read/ self - clear the power - good interrupt is masked when the part is initialized and during a norm al shutdown. 0 = no power - good failure has been detected on channel 3. 1 = power - good failure has been detected on channel 3. 1 pwrg2_int read/ self - clear the power - good interrupt is masked when the part is initialized and during a normal shutdown. 0 = no power - good failure has been detected on channel 2. 1 = power - good failure has been detected on channel 2. 0 pwrg1_int read/ self - clear the power - good interrupt is masked when the part is initialized and during a normal shutdown. 0 = no power - good failure has been detected on channel 1. 1 = power - good failure has been detected on channel 1.
data sheet ADP5050 rev. 0 | page 53 of 60 register 15: int_mas k ( interrupt mask confi guration), address 0 x 0f r egister 15 is used to mask or unmask various warnings for use by the interrupt (ni nt) pin. when any bit in this register is masked, the associated event does not trigger the nint pin. table 47. register 15 bit assignment s bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved mask_temp mask_lvin mask_pwrg4 mas k_pwrg3 mask_pwrg2 mask_pwrg1 table 48. int_mask register , bit function descriptions bits bit name access description [7:6] reserved r/w reserved. 5 mask_temp r/w 0 = temperature overheat warning does not trigger the interrupt p in (default). 1 = temperature overheat warning triggers the interrupt pin. 4 mask_lvin r/w 0 = low voltage input warning does not trigger the interrupt pin (default). 1 = low voltage input warning triggers the interrupt pin. 3 mask_pwrg4 r/w 0 = power - go od warning on channel 4 does not trigger the interrupt pin (default). 1 = power - good warning on channel 4 triggers the interrupt pin. 2 mask_pwrg3 r/w 0 = power - good warning on channel 3 does not trigger the interrupt pin (default). 1 = power - good warning on channel 3 triggers the interrupt pin. 1 mask_pwrg2 r/w 0 = power - good warning on channel 2 does not trigger the interrupt pin (default). 1 = power - good warning on channel 2 triggers the interrupt pin. 0 mask_pwrg1 r/w 0 = power - good warning on channe l 1 does not trigger the interrupt pin (default). 1 = power - good warning on channel 1 triggers the interrupt pin. register 17: default _set ( default reset), address 0 x 11 t h e write - only r egister 17 is used to reset all registers to their default values. ta ble 49. register 1 7 bit assignment s bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default_set[7:0] table 50. default_set register , bit function descriptions bits bit name access description [7:0] defaul t_set[7:0] w to reset all registers to their default values, write 0x7f to this register.
ADP5050 data sheet rev. 0 | page 54 of 60 factory programmable options table 51 through table 64 list the options that can be programmed into the ADP5050 when it is ordered from analog devices. for a list of the default options, see table 65 . to order a device with options o ther than the default options, contact your local analog devices sales or distribution representative . table 51. output voltage options for c hannel 1 ( fi xed o utput o ptions : 0.85 v to 1.6 v in 25 mv increments ) option description op tion 0 0.8 v adjustable output (default) option 1 0.85 v fixed output option 2 0.875 v fixed output option 30 1.575 v fixed output option 31 1.6 v fixed output table 52. output voltage options for c hannel 2 ( fi xed o utput o ptions : 3.3 v to 5.0 v in 3 00 mv/ 2 00 mv i ncrement s ) option description option 0 0.8 v adjustable output (default) option 1 3.3 v fixed output option 2 3.6 v fixed output option 3 3.9 v fixed output option 4 4.2 v fixed output option 5 4.5 v fixed ou tput option 6 4.8 v fixed output option 7 5.0 v fixed output table 53. output voltage options for c hannel 3 ( fi xed o utput o ptions : 1.2 v to 1.8 v in 100 mv i ncrement s ) option description option 0 0.8 v adjustable output (defaul t) option 1 1.2 v fixed output option 2 1. 3 v fixed output option 3 1. 4 v fixed output option 4 1.5 v fixed output option 5 1.6 v fixed output option 6 1.7 v fixed output option 7 1.8 v fixed output table 54. output voltage options for c hannel 4 ( fi xed o utput o ptions : 2.5 v to 5.5 v in 100 mv i ncrement s ) option description option 0 0.8 v adjustable output (default) option 1 2.5 v fixed output option 2 2.6 v fixed output option 30 5.4 v fixed output option 31 5.5 v fixed output table 55. pin 20 pwrgd/a0 pin options option description option 0 pwrgd pin for power - good output (default) option 1 a0 p in for i 2 c address setting
data sheet ADP5050 rev. 0 | page 55 of 60 table 56. pwrgd output options option des cription option 0 no monitoring of any channel option 1 monitor channel 1 output (default) option 2 monitor channel 2 output option 3 monitor channel 1 and channel 2 outputs option 4 monitor channel 3 output option 5 monitor channel 1 and channel 3 o utputs option 6 mo nitor channel 2 and channel 3 outputs option 7 monitor channel 1, channel 2, and channel 3 outputs option 8 monitor channel 4 output option 9 monitor channel 1 and channel 4 outputs option 10 monitor channel 2 and channel 4 outputs option 11 m onitor channel 1, channel 2, and channel 4 outputs option 12 monitor channel 3 and channel 4 outputs option 13 monitor channel 1 , channel 3 , and channel 4 outputs option 14 m onitor channel 2, channel 3, and channel 4 outputs option 15 monito r channel 1, channel 2, channel 3, and channel 4 outputs table 57. output discharge functionality options option description option 0 output discharge func tion disabled for all four buck regulators option 1 output discharge func t ion enabled for all four buck regulators (default) table 58. switching frequency options for c hannel 1 option description option 0 1 switching frequency set by the rt pin (default) option 1 ? swi tching frequency set by the rt pin table 59. switching frequency options for c hannel 3 option description option 0 1 swi tching frequency set by the rt pin (default) option 1 ? swi tching frequency set by the rt pin table 60. pin 43 sync/mode pin options o ption description option 0 f orced pwm/ automatic pwm/ psm mode setting with the ability to synchronize to an external clock (default) option 1 generate a clock signal equal to the master frequency set by the rt pin table 61 . hiccup protec tion options for the four buck regulator s option description option 0 hiccup protection ena bled for overcurrent events (default) option 1 hiccup protection disabled; frequency foldback protection only for overcurrent e vents table 62. short - circuit latch - o ff options for the four buck regulator s option description option 0 l atch - off function disabled for output short - circuit events (default) option 1 l atch - off function enabled for output short - circuit events
ADP5050 data sheet rev. 0 | page 56 of 60 table 63 . over voltage latch -o ff options for the four buck regulator s option description option 0 l atch - off functi on disabled for output over voltage event s (default) option 1 l atch - off funct ion enabled for output o ver voltage event s table 64. i 2 c address options option description option 0 0x48 (default) option 1 0x58 option 2 0x68 option 3 0x78 factory default opti ons table 65 lists the factory default option s programmed into the ADP5050 when the device is ordered (see the ordering guide ). to order the device with options other than the default options, contact your local an alog devices sales or distribution representative . table 51 through table 64 list all available options for the device. table 65 . factory default options option default value chan nel 1 output voltage 0.8 v adjustable output channel 2 output voltage 0.8 v adjustable output channel 3 output voltage 0.8 v adjustable output channel 4 output voltage 0.8 v adjustable output pwrgd pin (pin 20) function pwrgd pin for power - good output pwrgd pin (pin 20) output monitor channel 1 output output discharge function enabled for all four buck regulators switching frequency on channel 1 1 switching frequency set by the rt pin switching frequency on channel 3 1 switching frequency set by the rt pin sync/mode pin (pin 43) function f orced pwm/ automatic pwm/ psm mode setting with the ability to synchronize to an external clock hiccup protection enabled for overcurrent events short - circuit latch - off function disabled for output short - circui t events overvoltage latch - off function disabled for output over voltage events i 2 c address 0x48
data sheet ADP5050 rev. 0 | page 57 of 60 outline d imensions 1 0.50 bsc bot t om view top view pin 1 indic a t or 48 13 24 36 37 exposed pa d pin 1 indic a t or * 5.65 5.60 sq 5.55 0.50 0.40 0.30 sea ting plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.203 ref coplanarity 0.08 0.30 0.25 0.20 04-26-2013-c 7.10 7.00 sq 6.90 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.20 min * compliant to jedec standards mo-220-wkkd-2 with the exception of the exposed pad dimension. figure 69 . 48 - lead lead frame chip scale package [lfcsp_wq] 7 mm 7 mm body, very very thin quad (cp - 48 - 13) dimensions shown in millimeters ordering guide model 1 temperature range package description package option 2 ADP5050acpz -r7 ? 40 c to +125 c 48- lead lead frame chip scale package [lfcsp_wq] cp -48-13 ADP5050 - eval z evaluation board 1 z = ro hs compliant part. 2 table 65 lists the factory default options for the device. for a list of factory programmable options, see the factory programmable options section. to order a device with options oth er than the default options, contact your local analog devices sales or distribution representative .
ADP5050 data sheet rev. 0 | page 58 of 60 notes
data sheet ADP5050 rev. 0 | page 59 of 60 notes
ADP5050 data sheet rev. 0 | page 60 of 60 notes i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10899 - 0 - 5/13(0)

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